PCI Express Transfer

S

sebas

Guest
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda confused
I read about the PCIe protocol, I read the Xilinx documentation about thei
PCIe EP and I have a quesstion: I understand that the CPU, through the RC
controls the transfer (issuing a read or write command) but how does th
processor know when to issue the read command? I mean if I have a memory
on the EP side, that is updated every lets say 3 sec with new data how do
read the new data: does the software on the CPU side have to make rea
requests every 3 sec or does the EP signal an interrupt every time new dat
is available, or...?

Thanks,
Sebastian

---------------------------------------
Posted through http://www.FPGARelated.com
 
PCI Express does support interrupts so an interrupt could be generated whe
new data was available.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
In PCIe data transfers either reads or writes can be initiated from
either the main processor end or the card end. Interrupts unlike
conevntional PCI use an in-band message (data transfer) to signal an
interrupt on or off.

This gives you 2 principal options. The first is for a memory pointer
to written and stored on the card so it can move data directly to
memory. It might then use an interrupt to get the processor to process
the data.

The second, less efficient, way is to store data at the card end and
interrupt the processor to read the data and then move it to memory.

John Adair
Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development
Board.


On Feb 1, 4:31 pm, "sebas"
<tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda confused.
I read about the PCIe protocol, I read the Xilinx documentation about their
PCIe EP and I have a quesstion: I understand that the CPU, through the RC,
controls the transfer (issuing a read or write command) but how does the
processor know when to issue the read command? I mean if I have a memory,
on the EP side, that is updated every lets say 3 sec with new data how do I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time new data
is available, or...?

Thanks,
Sebastian          

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
 
Hey,

Thanks for the reply. What do you mean by not efficient? I only have fe
bytes to transmit (why I use PCIe it's a long story, let's just not ge
into in to it :) ) so I think the two situations described by you are th
same in this case. Am I right or didn't I understand your post?

Thanks

In PCIe data transfers either reads or writes can be initiated from
either the main processor end or the card end. Interrupts unlike
conevntional PCI use an in-band message (data transfer) to signal an
interrupt on or off.

This gives you 2 principal options. The first is for a memory pointer
to written and stored on the card so it can move data directly to
memory. It might then use an interrupt to get the processor to process
the data.

The second, less efficient, way is to store data at the card end and
interrupt the processor to read the data and then move it to memory.

John Adair
Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development
Board.


On Feb 1, 4:31=A0pm, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kind
confuse=
d.
I read about the PCIe protocol, I read the Xilinx documentation abou
the=
ir
PCIe EP and I have a quesstion: I understand that the CPU, through th
RC=
,
controls the transfer (issuing a read or write command) but how doe
the
processor know when to issue the read command? I mean if I have
memory,
on the EP side, that is updated every lets say 3 sec with new data ho
do=
I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time ne
da=
ta
is available, or...?

Thanks,
Sebastian =A0 =A0 =A0 =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
The read method is not efficient because often the processor takes in
the data and then writes it out to memory so 2 data movement actions.
That mechanism does vary a little with motherboard architecture and
that might be offloaded to a peripheral. If it's a small amount of
data it is fine to do it this way. For large amounts of data the card
end doing the initiation is much better and faster. It's a single
transfer and much less affected by other tasks that a CPU might be
running.

John Adair
Enterpoint Ltd.

On Feb 1, 11:11 pm, "andreiseb"
<andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
Hey,

Thanks for the reply. What do you mean by not efficient? I only have few
bytes to transmit (why I use PCIe it's a long story, let's just not get
into in to it :) ) so I think the two situations described by you are the
same in this case. Am I right or didn't I understand your post?

Thanks





In PCIe data transfers either reads or writes can be initiated from
either the main processor end or the card end. Interrupts unlike
conevntional PCI use an in-band message (data transfer) to signal an
interrupt on or off.

This gives you 2 principal options. The first is for a memory pointer
to written and stored on the card so it can move data directly to
memory. It might then use an interrupt to get the processor to process
the data.

The second, less efficient, way is to store data at the card end and
interrupt the processor to read the data and then move it to memory.

John Adair
Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development
Board.

On Feb 1, 4:31=A0pm, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda
confuse> >d.
I read about the PCIe protocol, I read the Xilinx documentation about
the> >ir
PCIe EP and I have a quesstion: I understand that the CPU, through the
RC> >,
controls the transfer (issuing a read or write command) but how does
the
processor know when to issue the read command? I mean if I have a
memory,
on the EP side, that is updated every lets say 3 sec with new data how
do> > I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time new
da> >ta
is available, or...?

Thanks,
Sebastian =A0 =A0 =A0 =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
 
Ok, I understand. The interrupt that has to pe generated is it a MS
generated at TLP level and I have to generate it through the user interfac
or is it a different "interrupt" automatically generated on a differen
layer and I don't have to worry about it. The reason I'm asking is becaus
I haven't found any reference to this issue in the Xlinix' EP User Guide.


The read method is not efficient because often the processor takes in
the data and then writes it out to memory so 2 data movement actions.
That mechanism does vary a little with motherboard architecture and
that might be offloaded to a peripheral. If it's a small amount of
data it is fine to do it this way. For large amounts of data the card
end doing the initiation is much better and faster. It's a single
transfer and much less affected by other tasks that a CPU might be
running.

John Adair
Enterpoint Ltd.

On Feb 1, 11:11=A0pm, "andreiseb"
andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
Hey,

Thanks for the reply. What do you mean by not efficient? I only hav
few
bytes to transmit (why I use PCIe it's a long story, let's just not get
into in to it :) ) so I think the two situations described by you ar
the
same in this case. Am I right or didn't I understand your post?

Thanks





In PCIe data transfers either reads or writes can be initiated from
either the main processor end or the card end. Interrupts unlike
conevntional PCI use an in-band message (data transfer) to signal an
interrupt on or off.

This gives you 2 principal options. The first is for a memory pointer
to written and stored on the card so it can move data directly to
memory. It might then use an interrupt to get the processor to process
the data.

The second, less efficient, way is to store data at the card end and
interrupt the processor to read the data and then move it to memory.

John Adair
Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development
Board.

On Feb 1, 4:31=3DA0pm, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda
confuse=3D
d.
I read about the PCIe protocol, I read the Xilinx documentatio
about
the=3D
ir
PCIe EP and I have a quesstion: I understand that the CPU, throug
the
RC=3D
,
controls the transfer (issuing a read or write command) but how does
the
processor know when to issue the read command? I mean if I have a
memory,
on the EP side, that is updated every lets say 3 sec with new dat
how
do=3D
I
read the new data: does the software on the CPU side have to mak
read
requests every 3 sec or does the EP signal an interrupt every tim
new
da=3D
ta
is available, or...?

Thanks,
Sebastian =3DA0 =3DA0 =3DA0 =3DA0 =3DA0

--------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0
Posted throughhttp://www.FPGARelated.com

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi,

Sorry if I'm posting a little bit out of topic here but I'm kind
confused.
I read about the PCIe protocol, I read the Xilinx documentation abou
their
PCIe EP and I have a quesstion: I understand that the CPU, through th
RC,
controls the transfer (issuing a read or write command) but how does the
processor know when to issue the read command? I mean if I have a memory,
on the EP side, that is updated every lets say 3 sec with new data how d
I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time ne
data
is available, or...?

Thanks,
Sebastian

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
You might get useful answers posting on the Xilinx Support Forum:
http://forums.xilinx.com/t5/PCI-Express/bd-p/PCIe


---------------------------------------
Posted through http://www.FPGARelated.com
 
The Xilinx EP guide gives details about generating interrupts. You just se
the appropriate signals on the core and an interrupt is generated.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Tue, 01 Feb 2011 10:31:22 -0600, "sebas"
<tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:

Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda confused.
I read about the PCIe protocol, I read the Xilinx documentation about their
PCIe EP and I have a quesstion: I understand that the CPU, through the RC,
controls the transfer (issuing a read or write command) but how does the
processor know when to issue the read command? I mean if I have a memory,
on the EP side, that is updated every lets say 3 sec with new data how do I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time new data
is available, or...?
Click to expand...
Given this specification I wouldn't even bother with interrupts.

I would have the host CPU read a status register sufficiently often (say twice a
second, or even faster!) and read the actual data whenever a "ready" bit was set
in the status register. The CPU can then write a register (possibly the same
status register) to clear the "ready" bit until next time.

- Brian
 
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