PCI Ethernet cards specification

[designer]

I wanted to get a detailed timing diagram (the amount of time it takes
to get a particular amount of data from the host to the MAC (of
ethernet)).... Can anyone point me any links/docs for this
purpose.....
Thanks,
Vittal

 

[LittleAlex]

On Mar 17, 7:24 am, designer <vittal.pa...@gmail.com> wrote:

I wanted to get a detailed timing diagram (the amount of time it takes
to get a particular amount of data from the host to the MAC (of
ethernet)).... Can anyone point me any links/docs for this
purpose.....
Thanks,
Vittal

Each and every PCI card is going to have different timing. Each and
every OS is going to have different timing. Each and every
motherboard is going to have different timing. Each and every CPU is
going to have different timing.

Lets see... Couple hundred different PCI cards, couple hundred
different motherboards, 50 or so CPUs and 10 or so different OS
(including service packs, etc.) How many of the 30 million different
combinations were you expecting to look at?

AL

 

[Andreas Ehliar]

On 2009-03-17, designer <vittal.patil@gmail.com> wrote:

I wanted to get a detailed timing diagram (the amount of time it takes
to get a particular amount of data from the host to the MAC (of
ethernet)).... Can anyone point me any links/docs for this
purpose.....

I was a supervisor for a final year project that created a PCI based
gigabit ethernet card a couple of years ago. You can find their report at
http://www.ep.liu.se/smash/record.jsf?searchId=1&pid=diva2:22746 .

You are probably interested in Appendix C of that report as it contains a
PCI bus trace of when the NIC is reading a packet via bus mastering DMA.

Unfortunately this appendix was created to show the problems with the PCI
bridge from OpenCores, so you can't just count cycles in this diagram. But
from the diagram we can see that it takes roughly 20 PCI bus cycles for a
read request from a PCI based NIC to be answered by the host chipset.


So a decent approximate answer to your question (based on only this
measured system) would be:

* 20 PCI cycles (plus a few more PCI cycles) to read the descriptor.
* 20 PCI cycles plus one PCI cycle per every 32-bit word in the packet.

(If you have a large packet you could approximate it with the number of
PCI cycles required to read the packet itself.)

Note that this is PCI bus timings. If you are interested in timing from a
user space program to the NIC you will have to measure the overhead of
the operating system as well...

/Andreas