PCell schematic + layout + VXL

[Sylvain]

Hello,

I'm using 5141usr5 and I've created a complete PCell with layout
symbol and schematic views.

I have an input, acting on the 3 views.
My symbol is a bit changed depending on the input value.
So are my layout view and schematic view.
It works.

But each time i run the VXL extraction (gen from source) I have a
window opening saying that my PCell schematic has changed before last
extraction, even if I have done a check and save of my top cell (the
one instanciating my PCell).
It seems normal because the extraction process should re-evaluate my
Pcell, but how to avoid the message ? (maybe a comparison of the PCell
state against its previous state, but it is not possible in the PCell
context).

Can anyone help me ?

Thanks in advance,
regards,

Sylvain

 

[Andrew Beckett]

Sylvain wrote, on 06/30/09 15:31:

Hello,

I'm using 5141usr5 and I've created a complete PCell with layout
symbol and schematic views.

I have an input, acting on the 3 views.
My symbol is a bit changed depending on the input value.
So are my layout view and schematic view.
It works.

But each time i run the VXL extraction (gen from source) I have a
window opening saying that my PCell schematic has changed before last
extraction, even if I have done a check and save of my top cell (the
one instanciating my PCell).
It seems normal because the extraction process should re-evaluate my
Pcell, but how to avoid the message ? (maybe a comparison of the PCell
state against its previous state, but it is not possible in the PCell
context).

Can anyone help me ?

Thanks in advance,
regards,

Sylvain

Hmm. That doesn't sound right.

What I'd do is first check that it's not solved in the latest ISR, and if not,
contact customer support.

A quick search didn't reveal anything obvious, and I don't really have time to
put together an example to try it out right now. So perhaps you can try this and
see what happens?

Regards,

Andrew.

 

[Sylvain]

On 6 juil, 11:42, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm>
wrote:

Sylvain wrote, on 06/30/09 15:31:





Hello,

I'm using 5141usr5 and I've created a complete PCell with layout
symbol and schematic views.

I have an input, acting on the 3 views.
My symbol  is a bit changed depending on the input value.
So are my layout view and schematic view.
It works.

But each time i run the VXL extraction (gen from source) I have a
window opening saying that my PCell schematic has changed before last
extraction, even  if I have done a check and save of my top cell (the
one instanciating my PCell).
It seems normal because the extraction process should re-evaluate my
Pcell, but how to avoid the message ? (maybe a comparison of the PCell
state against its previous state, but it is not possible in the PCell
context).

Can anyone help me ?

Thanks in advance,
regards,

Sylvain

Hmm. That doesn't sound right.

What I'd do is first check that it's not solved in the latest ISR, and if not,
contact customer support.

A quick search didn't reveal anything obvious, and I don't really have time to
put together an example to try it out right now. So perhaps you can try this and
see what happens?

Regards,

Andrew.- Masquer le texte des messages précédents -

- Afficher le texte des messages précédents -

Hello,
I've tried with 5141isr20080215 (the latest we have in 5141) and it
is still showing the same messages.
But in IC613 it is OK.

So let's close this issue.

Sylvain