pcb signal integrity check

This is the control board of my alternator simulator. I think we are
getting close to receiving a purchase order!

https://www.dropbox.com/s/wvyxwlwzou3thh9/T901_22.JPG?raw=1

It has high power, relay drivers, uP, FPGA, dram, ethernet, USB.

It goes close to the front panel in this:

https://www.dropbox.com/s/71whot11i312y63/P900_3d_3.jpg?raw=1

My homework assignment is to do the signal integrity checks. First
thing I had to do was shuffle the layer assignments and dielectric
stacks. That gets ugly on an 8-layer board. Looks like this will work:


L1 parts and traces
L2 traces
L3 ground
L4 power pours
L5 power pours
L6 power pours
L7 traces
L8 traces

The dielectric thicknesses will be 6, 16, 4, 4, 4, 16, 6. Yes that's
ugly. More layers always gets ugly. One trades reasonable trace widths
and impedances for crosstalk hazards.

I could add some edge-launch SMAs and a bunch of TDR test traces, to
see how badly the real board comes out.



--

John Larkin Highland Technology, Inc

The cork popped merrily, and Lord Peter rose to his feet.
"Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"