R
Robert Macy
Guest
Needed a quiet 3.3 Vdc on a PCB that had a noisy 4.1 Vdc available. So
designed an inexpensive way to get from 4.1 to 3.3's light load and
have almost no ripple/noise go through to the load, but just finished
analyzing using my custom approach, 'Other', and was not satisfied
with the impedance looking 'outwards' from the load, had an increase
impedance in the spectrum, a 2 ohm 'bump' . So...
Dropped in an LDO and followed it with a 10uF cap shown in the AppNote
for chip using the 3.3
Just went through the AC sweep looking into that supply, that is, back
into the LDO and cap's node, only to find ...Fairly high resistance,
but worse, there's a large spike of impedance, 200- 300 ohms, right in
the middle of the audio range! suddenly making the custome, 'other',
design function 100 times better.
Thinking about it, it would seem to me an ideal supply has low
resistance that then is rolled off with a bypass cap to catch all the
unknown high frequency demands. And, has no increase in impedance
anywhere over the spectrum.
But *every* 3 terminal regulator seems to show this increased output
impedance phenomenon, [upon close examination it's expected - caused
by an output that has 100 ohms with a closed loop around to lower the
effective resistance, at some point the loop can no longer lower
resistance and the resistance starts climbing, but as that happens,
the Z looks inductive and resonates with the filter cap exacerbating
the effect/problem.]
So two questions:
1) do all the chip makers know the supply will be this bad and design
for it?
[I didn't think so, because the chip makers specify PSRR, stating how
well the chip ignores signals on its power pin, but what if the
signals on the power pin come from the chip's own current demand?]
2) is there any inexpensive way to achieve 'ideal' power supply?
There are tons of products out there using active filtering, LDO's,
followed by caps, so either it is 'lived with' or solved. What am I
missing?
designed an inexpensive way to get from 4.1 to 3.3's light load and
have almost no ripple/noise go through to the load, but just finished
analyzing using my custom approach, 'Other', and was not satisfied
with the impedance looking 'outwards' from the load, had an increase
impedance in the spectrum, a 2 ohm 'bump' . So...
Dropped in an LDO and followed it with a 10uF cap shown in the AppNote
for chip using the 3.3
Just went through the AC sweep looking into that supply, that is, back
into the LDO and cap's node, only to find ...Fairly high resistance,
but worse, there's a large spike of impedance, 200- 300 ohms, right in
the middle of the audio range! suddenly making the custome, 'other',
design function 100 times better.
Thinking about it, it would seem to me an ideal supply has low
resistance that then is rolled off with a bypass cap to catch all the
unknown high frequency demands. And, has no increase in impedance
anywhere over the spectrum.
But *every* 3 terminal regulator seems to show this increased output
impedance phenomenon, [upon close examination it's expected - caused
by an output that has 100 ohms with a closed loop around to lower the
effective resistance, at some point the loop can no longer lower
resistance and the resistance starts climbing, but as that happens,
the Z looks inductive and resonates with the filter cap exacerbating
the effect/problem.]
So two questions:
1) do all the chip makers know the supply will be this bad and design
for it?
[I didn't think so, because the chip makers specify PSRR, stating how
well the chip ignores signals on its power pin, but what if the
signals on the power pin come from the chip's own current demand?]
2) is there any inexpensive way to achieve 'ideal' power supply?
There are tons of products out there using active filtering, LDO's,
followed by caps, so either it is 'lived with' or solved. What am I
missing?