PCB functional modeling

[canadianJaouk]

I am looking for suggestions for a functional board modeling flow.
Right now I model our boards in VHDL with real number models for
"analog" components. I model all components on the board including
primitives (resistors, caps, etc...)... What i am looking for is a
high level modeling flow where we're mostly interested in connectivity
(not electrical properties of the circuit).

The flow is essentially generating a VHDL netlist from a schematic
capture tool and running some perl scripts to make it "modeling
friendly".

The VHLD flows proves less than ideal, mainly because of
bidirectionality of relays, resistors and other such components. I
can make it work but it's always a headache to get the board model up
and running, and there is a lot of manual tweaking involved

So I am looking for suggestions to improve this flow. Mainly I would
like to know if I should use some other language than vhdl to make
this easier? Remember I need both std_logic and real numbers. I hear
a lot about systemC and systemVlog... would those be well suited
languages for this type of task? Any other suggestions?

Thanks!
-Jakub

 

[FMF]

Jakub,

Personally, I would stick with VHDL for now and consider VHDL-AMS in the
future. I have used VHDL for board-level verification for the past 15
years. It is not as simple as it could be but it works better than anything
else I have tried including Verilog.

Bidirectionality is a problem in VHDL (and in Verilog). We have some
bidirectional components on the FMF website (www.FreeModelFoundry.com) but,
they are not very robust.

Rick


canadianJaouk wrote:

I am looking for suggestions for a functional board modeling flow.
Right now I model our boards in VHDL with real number models for
"analog" components. I model all components on the board including
primitives (resistors, caps, etc...)... What i am looking for is a
high level modeling flow where we're mostly interested in connectivity
(not electrical properties of the circuit).

The flow is essentially generating a VHDL netlist from a schematic
capture tool and running some perl scripts to make it "modeling
friendly".

The VHLD flows proves less than ideal, mainly because of
bidirectionality of relays, resistors and other such components. I
can make it work but it's always a headache to get the board model up
and running, and there is a lot of manual tweaking involved

So I am looking for suggestions to improve this flow. Mainly I would
like to know if I should use some other language than vhdl to make
this easier? Remember I need both std_logic and real numbers. I hear
a lot about systemC and systemVlog... would those be well suited
languages for this type of task? Any other suggestions?

Thanks!
-Jakub