PCB Arcing/spark gap

B

Bob Stephens

Guest
A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA


Bob
--
"Just machines that make big decisions
programmed by fellas with compassion and vision."
-D. Fagen
(remove yomama)
 
On Tue, 04 May 2004 13:43:16 GMT, Bob Stephens wrote:

A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA

Bob
Click to expand...
We probably included links in that recent thread. You know, when you
go to google, if you click on the "groups" link and find this
group's archive, you can then select to search within this group
only. When I'm looking for a past thread, I'll search on the names
of the posters that I remember participating, the year, and as much
of the subject line as I can remember. Text in the body of the posts
can also be helpful. Ferinstance, I kinda remember someone posting a
link to an article that covered "crosstalk" between the traces, so I
might use that keyword, also.

--
Best Regards,
Mike
 
On Tue, 4 May 2004 11:30:03 -0400, Active8 wrote:

On Tue, 04 May 2004 13:43:16 GMT, Bob Stephens wrote:

A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA

Bob

We probably included links in that recent thread. You know, when you
go to google, if you click on the "groups" link and find this
group's archive, you can then select to search within this group
only. When I'm looking for a past thread, I'll search on the names
of the posters that I remember participating, the year, and as much
of the subject line as I can remember. Text in the body of the posts
can also be helpful. Ferinstance, I kinda remember someone posting a
link to an article that covered "crosstalk" between the traces, so I
might use that keyword, also.
Click to expand...
Thanks Mike. I wasn't aware of that feature in Google.

Bob
--
"Just machines that make big decisions
programmed by fellas with compassion and vision."
-D. Fagen
(remove yomama)
 
Bob Stephens <stephensyomamadigital@earthlink.net> wrote in message news:<56nr7ylj6783$.1j3bzwymx1jfx$.dlg@40tude.net>...
A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA
Bob
Click to expand...
Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim
 
"Jim Meyer" <jmeyer@nektonresearch.com> wrote in message
news:21ede509.0405041219.567f4499@posting.google.com...
Bob Stephens <stephensyomamadigital@earthlink.net> wrote in message
news:<56nr7ylj6783$.1j3bzwymx1jfx$.dlg@40tude.net>...
A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner
layers?
I've googled a fair amount and haven't really come up with anything.

TIA
Bob

Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim
Click to expand...
......and thereafter depends on the type/amount of crude deposited on the
board during assembly/testing/shipping/installation/operation of
product.....

Terry
 
On Wed, 5 May 2004 18:07:05 -0700, "Terry Given" <the_domes@xtra.co.nz> posted
this:

"Jim Meyer" <jmeyer@nektonresearch.com> wrote in message
news:21ede509.0405041219.567f4499@posting.google.com...
Bob Stephens <stephensyomamadigital@earthlink.net> wrote in message
news:<56nr7ylj6783$.1j3bzwymx1jfx$.dlg@40tude.net>...
A while back there was a discussion here about the minimum inter - trac
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner
layers?
I've googled a fair amount and haven't really come up with anything.

TIA
Bob

Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim

.....and thereafter depends on the type/amount of crude deposited on the
board during assembly/testing/shipping/installation/operation of
product.....

Terry

Note the "inner layers" part of the original post. That spec should be
Click to expand...
completely under control of the board manufacturer and not affected (much) by
subsequent processing of the board.

Jim
 
"James Meyer" <jmeyer@nowhere.com> wrote in message
news:6clh90puut8ho1q0r1irkk2i4sml2sdlqu@4ax.com...
On Wed, 5 May 2004 18:07:05 -0700, "Terry Given" <the_domes@xtra.co.nz
posted
this:

"Jim Meyer" <jmeyer@nektonresearch.com> wrote in message
news:21ede509.0405041219.567f4499@posting.google.com...
Bob Stephens <stephensyomamadigital@earthlink.net> wrote in message
news:<56nr7ylj6783$.1j3bzwymx1jfx$.dlg@40tude.net>...
A while back there was a discussion here about the minimum inter -
trac
distance to prevent unintentional spark gaps on PCB's. Anyone know of
a
table or a rule of thumb for spacing vs. applied voltage for inner
layers?
I've googled a fair amount and haven't really come up with anything.

TIA
Bob

Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim

.....and thereafter depends on the type/amount of crude deposited on the
board during assembly/testing/shipping/installation/operation of
product.....

Terry

Note the "inner layers" part of the original post. That spec should be
completely under control of the board manufacturer and not affected (much)
by
subsequent processing of the board.

Jim
Click to expand...
oops, didnt see that - you are quite right, the aforementioned crud issues
are irrelevant - assuming the inner layer traces come out (eg via/pad)
sufficiently far from each other.

I have however looked into this issue in particular, when looking at
designing planar smps transformers to run from 1kVdc. I never got a
satisfactory answer from the pcb manufacturers. IIRC Coombs' printed
circuits handbook gives you an idea of the dielectric strength of the
laminate itself, but the real issue is the dielectric strength of, and the
presence of voids in, the resin (b-stage prepreg IIRR). Making sure there
are no voids is the hard bit.

Terry
 
On Thu, 6 May 2004 11:15:06 -0700, "Terry Given" <the_domes@xtra.co.nz> posted
this:


oops, didnt see that - you are quite right, the aforementioned crud issues
are irrelevant - assuming the inner layer traces come out (eg via/pad)
sufficiently far from each other.

I have however looked into this issue in particular, when looking at
designing planar smps transformers to run from 1kVdc. I never got a
satisfactory answer from the pcb manufacturers. IIRC Coombs' printed
circuits handbook gives you an idea of the dielectric strength of the
laminate itself, but the real issue is the dielectric strength of, and the
presence of voids in, the resin (b-stage prepreg IIRR). Making sure there
are no voids is the hard bit.

Terry
Click to expand...
If high voltage is a sufficient issue, the board manufacturer can test
the breakdown voltage per board and only ship boards that pass the test. Of
course, you will have to pay a premium for that sort of testing.

Jim
 
"James Meyer" <jmeyer@nowhere.com> wrote in message
news:1nml90ti2i3e2jefitfits34m7pvmlphil@4ax.com...
On Thu, 6 May 2004 11:15:06 -0700, "Terry Given" <the_domes@xtra.co.nz
posted
this:


oops, didnt see that - you are quite right, the aforementioned crud
issues
are irrelevant - assuming the inner layer traces come out (eg via/pad)
sufficiently far from each other.

I have however looked into this issue in particular, when looking at
designing planar smps transformers to run from 1kVdc. I never got a
satisfactory answer from the pcb manufacturers. IIRC Coombs' printed
circuits handbook gives you an idea of the dielectric strength of the
laminate itself, but the real issue is the dielectric strength of, and
the
presence of voids in, the resin (b-stage prepreg IIRR). Making sure there
are no voids is the hard bit.

Terry


If high voltage is a sufficient issue, the board manufacturer can test
the breakdown voltage per board and only ship boards that pass the test.
Of
course, you will have to pay a premium for that sort of testing.

Jim
Click to expand...
individual testing was the only solution I could find, too. In the end I
didnt use a planar for that app - the total cost was too high, mostly due to
the type of switch I could use (1700V) restricting frequency, thereby fixing
Np,Nz at high values, which makes it difficult in planar.

cheers
Terry
 
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