Pbl uploading code on a Spartan II board

[Fargo]

hi,
I've bought an evaluation board with a Spartan II on it and made a JTAG
cable with the schematic :
http://www.embeddedtronics.com/public/Electronics/xiprog/schematics/xiprog_s
chematic.pdf
I'm using ISE webpack 6.1

My cable is detected :
Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
Driver windrvr.sys version = 5.0.5.1.
LPT base address = 0378h.
Cable connection established.
CB_PROGRESS_END - End Operation.
Elapsed time = 1 sec.

The pbl is when I try to retreive the boundary scan chain, Impact find a
bunch of 28 non xilinx devices.
In fact there is only the xc2s100 on the board....
When i've search on the web for a solution i've found that it may be
possible to change the LPT clock speed by adding an environment variable but
the speed is always set to 200kHz...

Thanks for your answers

Damien
(excuse me for my english)

 

[Fargo]

hi,
Never mind the question, i found the problem :
my cable from the dongle to the board was too long (about 1 metre) i've make
it shorter and everything was fine.
I post this solution to help if someone has the same pbl :

The pbl is when I try to retreive the boundary scan chain, Impact find a
bunch of 28 non xilinx devices.
In fact there is only the xc2s100 and a parallel prom on the board....

As I'm beginning with xilinx targets I may ask some other questions... be
ready
bye
Damien