pattern generator code

C

Chip

Guest
Hi,

Is there a way to generate a signal with an arbitrary repeating
pattern (say "10001") using only synthesizeable verilog or System
Verilog (or VHDL for that matter)?

I can hard code the desired pattern in a register and use that, but
there is no "clk" signal accessible to the module in which the
desired pattern needs to be generated.

An example wd be appreciated.

Thanks in advance
ChipHead
 
Chip wrote:
Hi,

Is there a way to generate a signal with an arbitrary repeating
pattern (say "10001") using only synthesizeable verilog or System
Verilog (or VHDL for that matter)?

I can hard code the desired pattern in a register and use that, but
there is no "clk" signal accessible to the module in which the
desired pattern needs to be generated.

An example wd be appreciated.

Thanks in advance
ChipHead
Click to expand...
You will be hard-pressed to make any sort of pattern generator with no
clock. Surely, unless the entire FPGA design is combinatorial, you can
find a clock somewhere.

You can also use a ring oscillator to create your own clock, though it's
not highly recommended.
-Kevin
 
Hi Kevin,

Thanks for your response.

I do have a clock accessible to the module in question, however it is
somewhat slow (ie not the fastest clock in the design).

Just following up on your post - how would I go about using the ring
oscillator?

Thanks in advance!



Kevin Neilson wrote:
Chip wrote:
Hi,

Is there a way to generate a signal with an arbitrary repeating
pattern (say "10001") using only synthesizeable verilog or System
Verilog (or VHDL for that matter)?

I can hard code the desired pattern in a register and use that, but
there is no "clk" signal accessible to the module in which the
desired pattern needs to be generated.

An example wd be appreciated.

Thanks in advance
ChipHead

You will be hard-pressed to make any sort of pattern generator with no
clock. Surely, unless the entire FPGA design is combinatorial, you can
find a clock somewhere.

You can also use a ring oscillator to create your own clock, though it's
not highly recommended.
-Kevin
Click to expand...
 
To clarify, since the accessible clock is not the fastest clock in the
design, we will generate a "slower" version of the pattern, which does
not meet the requirements.


Chip wrote:
Hi Kevin,

Thanks for your response.

I do have a clock accessible to the module in question, however it is
somewhat slow (ie not the fastest clock in the design).

Just following up on your post - how would I go about using the ring
oscillator?

Thanks in advance!



Kevin Neilson wrote:
Chip wrote:
Hi,

Is there a way to generate a signal with an arbitrary repeating
pattern (say "10001") using only synthesizeable verilog or System
Verilog (or VHDL for that matter)?

I can hard code the desired pattern in a register and use that, but
there is no "clk" signal accessible to the module in which the
desired pattern needs to be generated.

An example wd be appreciated.

Thanks in advance
ChipHead

You will be hard-pressed to make any sort of pattern generator with no
clock. Surely, unless the entire FPGA design is combinatorial, you can
find a clock somewhere.

You can also use a ring oscillator to create your own clock, though it's
not highly recommended.
-Kevin
Click to expand...
 
Chip <ekrads@gmail.com> writes:

To clarify, since the accessible clock is not the fastest clock in the
design, we will generate a "slower" version of the pattern, which does
not meet the requirements.

....

Just following up on your post - how would I go about using the ring
oscillator?

....
Kevin Neilson wrote:
....
You can also use a ring oscillator to create your own clock, though it's
not highly recommended.
-Kevin
Click to expand...
Your real solution is to go back to whoever is specifying the
interface and getting them to give you a clock of the appropriate
speed. If they want something at a particular frequency, they should
give you a clock with that frequency, so that you are in synch with
that clock. Doing otherwise is simply likely to create a buggy
design.

However, to answer your question, as I recall, a ring oscillator is
some circuitry (often a combinatorial loop) where the input circles
around in the circuit but never stabilizes, generating a series of
ones and zeros. A simple one can be created (at least in theory) by
tying the output of an inverter to its input, if the value is one, it
must be zero, and vice-versa. Note, if you try to simulate that
circuit in Verilog, it is likely to get stuck with the clock never
advancing, because the circuit doesn't stabilize. Depending on how
said inverter is implemented at the transistor level, it may or may
not work as a ring oscillator. There are many other potential issues,
particularly if the rise and fall times of such gates are not the
same. Also, imagine if your hand-created clock rose and fell during
the setup or hold times of the clock your circuit is supposed to synch
to. The basic point is that in most circumstances you don't want to
create "clocks" on the fly out of combinations of digital circuits
when you don't have to. There are times when one has to, but if there
is a clock of the appropriate speed in the design, one doesn't have
to.
 
On Tue, 15 Jul 2008 19:51:34 -0400, Chris F Clark
<cfc@shell01.TheWorld.com> wrote:
However, to answer your question, as I recall, a ring oscillator is
some circuitry (often a combinatorial loop) where the input circles
around in the circuit but never stabilizes, generating a series of
ones and zeros. A simple one can be created (at least in theory) by
tying the output of an inverter to its input, if the value is one, it
must be zero, and vice-versa.
Click to expand...
A single inverter would oscillate too fast to be of any practical use.
It's better to make a ring out of an odd number of inverters by taking
the total minimum/maximum delay of the ring to get a useful clock.

Note, if you try to simulate that
circuit in Verilog, it is likely to get stuck with the clock never
advancing, because the circuit doesn't stabilize.
Click to expand...
This is only a problem if the oscillation happens in zero time. If one
models a real inverter ie. one with positive delay, time advances in
the simulation and other events get processed.

In the absence of any other reasonable solution, if it's absolutely
necessary a ring oscillator made from logic gates can be used but
because a calibration circuit for such a design is difficult (but not
impossible) to implement, output clock frequency variation across PVT
changes would probably be too much to be of any practical use.
 
On Jul 15, 4:51 pm, Chris F Clark <c...@shell01.TheWorld.com> wrote:
Chip <ekr...@gmail.com> writes:
To clarify, since the accessible clock is not the fastest clock in the
design, we will generate a "slower" version of the pattern, which does
not meet the requirements.

...

Just following up on your post - how would I go about using the ring
oscillator?

...
Kevin Neilson wrote:
...
You can also use a ring oscillator to create your own clock, though it's
not highly recommended.
-Kevin

Your real solution is to go back to whoever is specifying the
interface and getting them to give you a clock of the appropriate
speed.  If they want something at a particular frequency, they should
give you a clock with that frequency, so that you are in synch with
that clock.  Doing otherwise is simply likely to create a buggy
design.

However, to answer your question, as I recall, a ring oscillator is
some circuitry (often a combinatorial loop) where the input circles
around in the circuit but never stabilizes, generating a series of
ones and zeros.  A simple one can be created (at least in theory) by
tying the output of an inverter to its input, if the value is one, it
must be zero, and vice-versa.  Note, if you try to simulate that
circuit in Verilog, it is likely to get stuck with the clock never
advancing, because the circuit doesn't stabilize.  Depending on how
said inverter is implemented at the transistor level, it may or may
not work as a ring oscillator.  There are many other potential issues,
particularly if the rise and fall times of such gates are not the
same.  Also, imagine if your hand-created clock rose and fell during
the setup or hold times of the clock your circuit is supposed to synch
to.  The basic point is that in most circumstances you don't want to
create "clocks" on the fly out of combinations of digital circuits
when you don't have to.  There are times when one has to, but if there
is a clock of the appropriate speed in the design, one doesn't have
to.- Hide quoted text -

- Show quoted text -
Click to expand...
Thanks for the excellent explanations Chris and Kevin!!
 
thanks muzaffer.

Muzaffer Kal wrote:
On Tue, 15 Jul 2008 19:51:34 -0400, Chris F Clark
cfc@shell01.TheWorld.com> wrote:
However, to answer your question, as I recall, a ring oscillator is
some circuitry (often a combinatorial loop) where the input circles
around in the circuit but never stabilizes, generating a series of
ones and zeros. A simple one can be created (at least in theory) by
tying the output of an inverter to its input, if the value is one, it
must be zero, and vice-versa.

A single inverter would oscillate too fast to be of any practical use.
It's better to make a ring out of an odd number of inverters by taking
the total minimum/maximum delay of the ring to get a useful clock.

Note, if you try to simulate that
circuit in Verilog, it is likely to get stuck with the clock never
advancing, because the circuit doesn't stabilize.

This is only a problem if the oscillation happens in zero time. If one
models a real inverter ie. one with positive delay, time advances in
the simulation and other events get processed.

In the absence of any other reasonable solution, if it's absolutely
necessary a ring oscillator made from logic gates can be used but
because a calibration circuit for such a design is difficult (but not
impossible) to implement, output clock frequency variation across PVT
changes would probably be too much to be of any practical use.
Click to expand...
 
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