Path Tracing in Layout

[saby]

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[S. Badel]

could possibly do this with geomGetNet() if you know or assign a net name
to that particular net

"saby" <s_abhi23@yahoo.com> wrote in message
news:9f1a8bc2.0404052039.beb68c5@posting.google.com...

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[Diva Physical Verificatio]

Diva does not have anything for doing this. You might be able to get
what you want by writing some SKILL around Diva.

The first step would be to extract the complete chip at the simplest
level: no parasitics, nothing more than finding the connectivity.

Then you can have a SKILL procedure that traces the connectivity in the
extracted view from your starting pin through all branches until you
find one that gets you to the end pin. This assumes you have some
information about inputs and output of the standard cells. Perhaps the
pin direction, if set, is enough for this.

Now that you know the instances and nets that form the path, you can
write some marker shapes into the layout and run extraction again. The
marker shapes would be used to limit the interconnect to the shapes
which are part of the path. More shapes may be needed if you are trying
to do parasitic resistance and capacitance. This step is very murky
since it depends heavily upon what you are trying to do with the path.

On 5 Apr 2004 21:39:38 -0700, s_abhi23@yahoo.com (saby) wrote:

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[Andrew Beckett]

You could use the mark net command (in the layout editor) to highlight the net - but I'm not sure
that's quite what you're after here...

Andrew.

On 5 Apr 2004 21:39:38 -0700, s_abhi23@yahoo.com (saby) wrote:

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Partha]

Cant we use the MSPS to get selected path parsitics from the graphical
extracted view that is created....

s_abhi23@yahoo.com (saby) wrote in message news:<9f1a8bc2.0404052039.beb68c5@posting.google.com>...

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[saby]

Actually this very close to what I was looking for. Thanks. I do know
the direction and pin names of the standard cells (along the path). I
am not an expert in skill programming but I will try and follow the
steps you have mentioned. Also, in the end I am interested in getting
a detailed RC parasitics of the particular path. I was thinking that
some tool in cadence already does this, because of need to verify
switching paths for signal integrity analysis and to make sure that no
violations occur. Isn't that true??

Regards
-Saby.

Diva Physical Verification <diva@cadence.com> wrote in message news:<1gp47092isauhdkea4mfqitnu0f08qnbmc@4ax.com>...

Diva does not have anything for doing this. You might be able to get
what you want by writing some SKILL around Diva.

The first step would be to extract the complete chip at the simplest
level: no parasitics, nothing more than finding the connectivity.

Then you can have a SKILL procedure that traces the connectivity in the
extracted view from your starting pin through all branches until you
find one that gets you to the end pin. This assumes you have some
information about inputs and output of the standard cells. Perhaps the
pin direction, if set, is enough for this.

Now that you know the instances and nets that form the path, you can
write some marker shapes into the layout and run extraction again. The
marker shapes would be used to limit the interconnect to the shapes
which are part of the path. More shapes may be needed if you are trying
to do parasitic resistance and capacitance. This step is very murky
since it depends heavily upon what you are trying to do with the path.

On 5 Apr 2004 21:39:38 -0700, s_abhi23@yahoo.com (saby) wrote:

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[Diva Physical Verificatio]

My focus is Diva so I can't be sure, but I seem to recall one of the
products Cadence acquired when Simplex was bought has something to do
with signal integrity analysis.

On 6 Apr 2004 22:36:22 -0700, s_abhi23@yahoo.com (saby) wrote:

Actually this very close to what I was looking for. Thanks. I do know
the direction and pin names of the standard cells (along the path). I
am not an expert in skill programming but I will try and follow the
steps you have mentioned. Also, in the end I am interested in getting
a detailed RC parasitics of the particular path. I was thinking that
some tool in cadence already does this, because of need to verify
switching paths for signal integrity analysis and to make sure that no
violations occur. Isn't that true??

Regards
-Saby.

Diva Physical Verification <diva@cadence.com> wrote in message news:<1gp47092isauhdkea4mfqitnu0f08qnbmc@4ax.com>...
Diva does not have anything for doing this. You might be able to get
what you want by writing some SKILL around Diva.

The first step would be to extract the complete chip at the simplest
level: no parasitics, nothing more than finding the connectivity.

Then you can have a SKILL procedure that traces the connectivity in the
extracted view from your starting pin through all branches until you
find one that gets you to the end pin. This assumes you have some
information about inputs and output of the standard cells. Perhaps the
pin direction, if set, is enough for this.

Now that you know the instances and nets that form the path, you can
write some marker shapes into the layout and run extraction again. The
marker shapes would be used to limit the interconnect to the shapes
which are part of the path. More shapes may be needed if you are trying
to do parasitic resistance and capacitance. This step is very murky
since it depends heavily upon what you are trying to do with the path.

On 5 Apr 2004 21:39:38 -0700, s_abhi23@yahoo.com (saby) wrote:

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

 

[fogh]

saby wrote:

Hi.
I am interested in extracting only a selective path from the entire
layout (in Virtuoso) using diva. I have the layout in terms of
standard cells. All I know is that a path starts at some pin/label and
ends at another pin/label. Can I just extract that particular path?

Regards
-saby

Do you really need to manipulate the database and do this in diva ?

If not, you could make your life easier if you can work on a schematic (import verilog if necessary). You can then extract parasitic series resistance, define a simple simulation, and then do out-of-context probing to follow where current is going. Otherwise, there must be a proper CS-like way of doing this: extract the path of least resistance, then remove it and extract again, until there is no path left, but I would not know how to attack it.