Path extraction using Assura RCX

[Aby]

Hi All:
I am interested in performing detailed spice simulations on a selective
path in my chip. Is there a way I can extract a selective path
(starting at a pin and ending at another pin) using Assura RCX (or
related tool). If so can someone guide me how this can be done?
Best regards
-Aby

 

[S. Badel]

If you look into the manual, in the section dealing with RCX, you will see there are different
options for parasitics extraction :
Full Chip All Nets
Full Chip Selected Nets
Selected Nets Proper
Selected Paths
Excluded Nets
With the third being what you're looking for I guess. Look into the manual again for detailled
explanation of each of these modes.
Hope this helps,
stéphane



Aby wrote:

Hi All:
I am interested in performing detailed spice simulations on a selective
path in my chip. Is there a way I can extract a selective path
(starting at a pin and ending at another pin) using Assura RCX (or
related tool). If so can someone guide me how this can be done?
Best regards
-Aby

 

[Svenn Are Bjerkem]

Andrew Beckett wrote:

In IC5033 onwards you can do File->Import->Netlist View which will do exactly
this.

I just had to try this feature, and tried to import my av_extracted view
to a schematic, and got following message:

CellViewType "maskLayout" for cell "TR_ampcontrol, lib "wk_bjerkem" is
not an eligible viewType. Exiting.

--
Svenn

 

[Andrew Beckett]

Ah, beat me to it. I was just reminding myself of the full list of choices,
and Stephane got there first (thanks!)

Andrew.

On Thu, 03 Feb 2005 10:36:16 +0100, "S. Badel"
<stephane.badel@REMOVETHISepfl.ch> wrote:

If you look into the manual, in the section dealing with RCX, you will see there are different
options for parasitics extraction :
Full Chip All Nets
Full Chip Selected Nets
Selected Nets Proper
Selected Paths
Excluded Nets
With the third being what you're looking for I guess. Look into the manual again for detailled
explanation of each of these modes.
Hope this helps,
stéphane



Aby wrote:
Hi All:
I am interested in performing detailed spice simulations on a selective
path in my chip. Is there a way I can extract a selective path
(starting at a pin and ending at another pin) using Assura RCX (or
related tool). If so can someone guide me how this can be done?
Best regards
-Aby

 

[fogh]

You still have a chance to tell him about MSPS with the "from schematic"
filter option . But the list is shorter. Less convincing in an RTFM answer

Andrew Beckett wrote:

Ah, beat me to it. I was just reminding myself of the full list of choices,
and Stephane got there first (thanks!)

Andrew.

On Thu, 03 Feb 2005 10:36:16 +0100, "S. Badel"
stephane.badel@REMOVETHISepfl.ch> wrote:


If you look into the manual, in the section dealing with RCX, you will see there are different
options for parasitics extraction :
Full Chip All Nets
Full Chip Selected Nets
Selected Nets Proper
Selected Paths
Excluded Nets
With the third being what you're looking for I guess. Look into the manual again for detailled
explanation of each of these modes.
Hope this helps,
stéphane



Aby wrote:

Hi All:
I am interested in performing detailed spice simulations on a selective
path in my chip. Is there a way I can extract a selective path
(starting at a pin and ending at another pin) using Assura RCX (or
related tool). If so can someone guide me how this can be done?
Best regards
-Aby

 

[Svenn Are Bjerkem]

I just got a problem that is also Assura RCX related, but a bit
different. As I come from the front end side I have very little
experience with backend.

To simulate loop-gain I have inserted a voltage source in series in my
schematics and set lvsignore to true. The layout has been created
without the series source and in order to get an lvs clean circuit I
have cut the connection where the source is inserted. Assura runs fine
and creates an av_extracted view. So far so good.

Now I open the av_extracted view and place a voltage source in the cut,
just like assura would place a parasitic resistor during rc-extraction.
I now hoped that I would be able to create a netlist from this
av_extracted with the additional voltage source, but I get a failure
message stating that av_extracted has been modified since last
extraction. (Which is true beacuse I added the v-source) and that I
should check and save if it is a schematic view. I cannot find a way to
convince the system that everything is ok.

Maybe I have misunderstood something here.

--
Svenn

 

[S. Badel]

Yes this happens. A clever way to do it would be to make this source external
to your circuit (ie make two pins were you want to connect the source, then
create a testbench with a source in between these pins).

If however you want to do it the way you described, you can type
auLvsFixTimeStamps( geGetEditCellView() ) && dbSave( geGetEditCellView() )
after having added the source.
this should fix the modification/extraction mismatch.

good luck,
stéphane

Svenn Are Bjerkem wrote:

I just got a problem that is also Assura RCX related, but a bit
different. As I come from the front end side I have very little
experience with backend.

To simulate loop-gain I have inserted a voltage source in series in my
schematics and set lvsignore to true. The layout has been created
without the series source and in order to get an lvs clean circuit I
have cut the connection where the source is inserted. Assura runs fine
and creates an av_extracted view. So far so good.

Now I open the av_extracted view and place a voltage source in the cut,
just like assura would place a parasitic resistor during rc-extraction.
I now hoped that I would be able to create a netlist from this
av_extracted with the additional voltage source, but I get a failure
message stating that av_extracted has been modified since last
extraction. (Which is true beacuse I added the v-source) and that I
should check and save if it is a schematic view. I cannot find a way to
convince the system that everything is ok.

Maybe I have misunderstood something here.

 

[Svenn Are Bjerkem]

Hi Stépane,

you wrote:

Yes this happens. A clever way to do it would be to make this source
external
to your circuit (ie make two pins were you want to connect the source, then
create a testbench with a source in between these pins).

This advice I got from all my colleagues that I have asked for help on
the problem. I think I have learned a very important lesson.

If however you want to do it the way you described, you can type
auLvsFixTimeStamps( geGetEditCellView() ) && dbSave( geGetEditCellView() )
after having added the source.
this should fix the modification/extraction mismatch.

I was not able to use the geGetEditCellView() functions, so I searched
on sourcelink and found another way:
cv=hiGetCurrentWindow()->cellView
auLvsFixTimeStamps( cv )
dbSave( cv )

Now I can create a netlist with the symbol of a dc-source in my layout.
Problem is that it is not connected to any net, even if I have placed my
metal so that it touches the pins of the vdc symbol. I think there are
some more things that I don't understand regarding manipulating
extracted views.

Anybody know how to connect a piece of metal to a schematic symbol?

--
Svenn

 

[S. Badel]

Svenn,

If in the layout you select any of the symbols and type in the CIW
car(geGetSelSet())~>instTerms~>net~>name
you will see that the net names are correct. This has been set by the layout extractor when it built
the database (the cellview). If you insert a component and do the same with it, you will see your
component has no instTerms yet. This means, it's part of the database but not yet connected to
anything. The schematic editor does the job of connecting the components in the database according
to the wires you draw, but hey we're not in the schematic editor right?
You can however manipulate the databse "by hand" using all of the db functions.
for instance,
cv=getGetEditCellView()
inst=car(geGetSelSet()) ; or: inst=dbFindAnyInstByName(cv, "my_inst_name")
net=dbFindNetByName(cv, "my_net_name")
term=dbFindTermByName( inst~>master, "PLUS" )
dbCreateInstTerm( net inst term )
net=dbFindNetByName(cv, "my_other_net_name")
term=dbFindTermByName( inst~>master, "MINUS" )
dbCreateInstTerm( net inst term )
auLvsFixTimeStamps(cv)
dbSave(cv)
Now if you create a netlist, your component will be connected.
This lets us appreciate the comfort of using a schematic editor instead of having to type all this
by hand And shows how a schematic is in fact no more than a graphical display of a netlist.
Whenever one clicks "check and save" in schematic editor, behind the scenes the connectivity is
extracted and instance terminals are connected to the proper net. That's why it can then be
netlisted. The code above is actually doing manually what the schematic editor would have done for us...

I hope this will convince you to turn to the schematic version of the trick...

cheers,

stéphane

Svenn Are Bjerkem wrote:

Hi Stépane,

you wrote:

Yes this happens. A clever way to do it would be to make this source
external
to your circuit (ie make two pins were you want to connect the source,
then
create a testbench with a source in between these pins).


This advice I got from all my colleagues that I have asked for help on
the problem. I think I have learned a very important lesson.


If however you want to do it the way you described, you can type
auLvsFixTimeStamps( geGetEditCellView() ) && dbSave(
geGetEditCellView() )
after having added the source.
this should fix the modification/extraction mismatch.


I was not able to use the geGetEditCellView() functions, so I searched
on sourcelink and found another way:
cv=hiGetCurrentWindow()->cellView
auLvsFixTimeStamps( cv )
dbSave( cv )

Now I can create a netlist with the symbol of a dc-source in my layout.
Problem is that it is not connected to any net, even if I have placed my
metal so that it touches the pins of the vdc symbol. I think there are
some more things that I don't understand regarding manipulating
extracted views.

Anybody know how to connect a piece of metal to a schematic symbol?

 

[Andrew Beckett]

On Mon, 07 Feb 2005 11:22:12 +0100, Svenn Are Bjerkem <svenn.are@bjerkem.de>
wrote:

I was not able to use the geGetEditCellView() functions, so I searched
on sourcelink and found another way:
cv=hiGetCurrentWindow()->cellView
auLvsFixTimeStamps( cv )
dbSave( cv )

Not sure why geGetEditCellView() didn't work - might be due to the Assura
"feature" which means that it tends to unset the current window with alarming
regularity.

Now I can create a netlist with the symbol of a dc-source in my layout.
Problem is that it is not connected to any net, even if I have placed my
metal so that it touches the pins of the vdc symbol. I think there are
some more things that I don't understand regarding manipulating
extracted views.

Anybody know how to connect a piece of metal to a schematic symbol?

Just touching the metal won't make it connected, since there is nothing to
extract the connectivity.

When you create the symbol, you'll need to create instTerm objects to connect
the terminals of the source to the appropriate net.

That would be done with two calls to dbCreateInstTerm() - passing the
dbId of the net you're connecting to, the dbId of the source instance,
and the dbId of the source terminal. Assuming that you have the instance
in a variable "inst", and are PLUS to "A" and MINUS to "B", it would be:

dbCreateInstTerm(dbFindNetByName(cv "A") inst
dbFindTermByName(inst~>master "PLUS")
)
dbCreateInstTerm(dbFindNetByName(cv "B") inst
dbFindTermByName(inst~>master "MINUS")
)

Or something like that...

Regards,

Andrew.

 

[Svenn Are Bjerkem]

S. Badel wrote:

Now if you create a netlist, your component will be connected.
This lets us appreciate the comfort of using a schematic editor instead
of having to type all this by hand And shows how a schematic is in
fact no more than a graphical display of a netlist. Whenever one clicks
"check and save" in schematic editor, behind the scenes the connectivity
is extracted and instance terminals are connected to the proper net.
That's why it can then be netlisted. The code above is actually doing
manually what the schematic editor would have done for us...

I hope this will convince you to turn to the schematic version of the
trick...

T h i s i s s i m p l y a m a z i n g ! !

The schematic editor may be a tool that take some stress away from us,
but comp.cad.cadence take over where composer let go. I could now
perfectly insert any component into my loop break; that this is bad
design methodology is clear: Kids don't do this at home; but when the
shit has hit the fan it is nice to know how to work around it temporarily.

Thankful regards,
--
Svenn

 

[S. Badel]

The schematic editor may be a tool that take some stress away from us

I like this sentence! Let's thankfully praise our virtual psychiatrist

Btw I'd wonder what would happen if you changed the view type to schematic and
try to edit it with the shematic editor...

And FYI I found some time ago a script on sourcelink which processed an extracted view,
creating a schematic with the same components and connectivity, thus editable with the
composer.

stéphane


Svenn Are Bjerkem wrote:

S. Badel wrote:

Now if you create a netlist, your component will be connected.
This lets us appreciate the comfort of using a schematic editor
instead of having to type all this by hand And shows how a
schematic is in fact no more than a graphical display of a netlist.
Whenever one clicks "check and save" in schematic editor, behind the
scenes the connectivity is extracted and instance terminals are
connected to the proper net. That's why it can then be netlisted. The
code above is actually doing manually what the schematic editor would
have done for us...

I hope this will convince you to turn to the schematic version of the
trick...


T h i s i s s i m p l y a m a z i n g ! !

The schematic editor may be a tool that take some stress away from us,
but comp.cad.cadence take over where composer let go. I could now
perfectly insert any component into my loop break; that this is bad
design methodology is clear: Kids don't do this at home; but when the
shit has hit the fan it is nice to know how to work around it temporarily.

Thankful regards,

 

[Andrew Beckett]

Stephane,

On Tue, 08 Feb 2005 11:52:39 +0100, "S. Badel"
<stephane.badel@REMOVETHISepfl.ch> wrote:

The schematic editor may be a tool that take some stress away from us

I like this sentence! Let's thankfully praise our virtual psychiatrist

Btw I'd wonder what would happen if you changed the view type to schematic and
try to edit it with the shematic editor...

It's not that easy to change the viewType - but I think this is probably not a
good idea. For a start, the schematic extractor will struggle to make the
connectivity when you do a check-and-save!

And FYI I found some time ago a script on sourcelink which processed an extracted view,
creating a schematic with the same components and connectivity, thus editable with the
composer.

In IC5033 onwards you can do File->Import->Netlist View which will do exactly
this.

Andrew.