passthroughs

[raphfrk]

I am pretty sure that this is impossible, but figured that I might as
well ask:

Is there a way to wire up inout ports as a passthrough in verilog?

For example:

module passthrough( a, b );

inout a;
inout b;

assign a=(b!==1'bz)?b:1'bz;
assign b=(a!==1'bz)?a:1'bz;

endmodule

Obviously, the above wouldn't work. The desired effect is that a and b
are effectively shorted to each other and that the data can pass both
ways.

 

[Jonathan Bromley]

On 16 Jan 2007 03:03:42 -0800, "raphfrk" <raphfrk@netscape.net> wrote:

Is there a way to wire up inout ports as a passthrough in verilog?

Yes. Take a look at the tran and tranif1 primitives.

For example:

module passthrough( a, b );

inout a;
inout b;

assign a=(b!==1'bz)?b:1'bz;
assign b=(a!==1'bz)?a:1'bz;

endmodule

Obviously, the above wouldn't work. The desired effect is that a and b
are effectively shorted to each other and that the data can pass both
ways.

So, you just need

tran(a,b);

or, better,

tranif1(a,b,enable);

so that a and b are shorted together if enable is true, and isolated
if enable is false.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Peter Riocreux]

Easier is:

module passthrough (a, a);
inout a;
endmodule

or something like that, which used to work in most (if not all) simulators,
but I have no idea what synthesis tools or other parts of the toolflow would
do with it.

It works because they are the same port and therefore connected together.

Obviously connection must be by position rather than name, but ....

Peter

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:3kfpq25nkl0bbtrlrr3vi7btbtredfv28k@4ax.com...

On 16 Jan 2007 03:03:42 -0800, "raphfrk" <raphfrk@netscape.net> wrote:

Is there a way to wire up inout ports as a passthrough in verilog?

Yes. Take a look at the tran and tranif1 primitives.

For example:

module passthrough( a, b );

inout a;
inout b;

assign a=(b!==1'bz)?b:1'bz;
assign b=(a!==1'bz)?a:1'bz;

endmodule

Obviously, the above wouldn't work. The desired effect is that a and b
are effectively shorted to each other and that the data can pass both
ways.

So, you just need

tran(a,b);

or, better,

tranif1(a,b,enable);

so that a and b are shorted together if enable is true, and isolated
if enable is false.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[raphfrk]

Jonathan Bromley wrote:

On 16 Jan 2007 03:03:42 -0800, "raphfrk" <raphfrk@netscape.net> wrote:

Is there a way to wire up inout ports as a passthrough in verilog?

Yes. Take a look at the tran and tranif1 primitives.

Gah, how did I miss those.

Thanks alot.

<snip example>

 

raphfrk wrote:

Is there a way to wire up inout ports as a passthrough in verilog?

This is actually trivial in Verilog. You could use a tran to connect
them,
but it is easier to just short them together. One usual way of doing
this
is with a module like

module passthrough(a,a);
inout a;
endmodule

This module can only be connected by position, since the names of
the ports are not unique. Also, some tools might object to both ports
having the same name. You can deal with this by using a slightly
more complex module declaration:

module passthrough(.a(c), .b(c));
inout c;
endmodule

Now you have two ports with external names of a and b, which are
internally connected to the same net c. You can now connect to
these two ports by position or by name.

You can also declare the inout port to be a vector, possibly with
a parameterized width, if you need to pass a vector through. If
you don't want to rely on an implicit net declaration for the port, you
can also add an explicit wire declaration for it in addition to the
inout
declaration. For example

module passthrough (.a(c), .b(c));
parameter width = 1;
inout [width-1:0] c;
wire [width-1:0] c;
endmodule

And then to instantiate it with a width and by name

wire [7:0] w1, w2;

passthrough #(.width(8)) p(.a(w1), .b(w2));