Passing V2K, SV attributes

[Amal]

Here is another frustrating missing feature in V2K and SV. I have a
dilemma and it relates to the way attributes are defined in Verilog
200x and SystemVerilog. Basically I would like to attach an attribute
to a declaration inside a module. The attribute could vary from
instance to instance. I thought I use macro defines, but couldn't
think of a way to do it per instance.

I don't want to start language wars again, but I DO NOT understand WHY
simple features like this or so many other things that I can think of
in VHDL is still not even supported in SystemVerilog!!!

Here is what I like to do in Verilog and be able to change attribute_1
and attribute_2 values per instance:

---start-verilog-code---------
module xyx;

// This
(* keep, attribute_1 = "value_1" *)
reg a;

// OR
reg b /* synthesis keep, attribute_2 = "value_2" */;

endmodule //:xyx
---end-verilog-code---------


In VHDL this is possible and pretty easy to do:

---start-vhdl-code---------
entity xyz is
generic ( attr1 : string := "value_1"; attr2 : string :=
"value_2" );
port (
ia : in bit;
oa : out bit;
ib : in bit_vector(1 downto 0);
ob : out bit_vector(1 downto 0)
);
end entity xyz;

architecture rtl of xyz is
signal a : bit;
signal b : bit_vector(1 downto 0);

attribute attribute_1 : string;
attribute attribute_1 of a : signal is attr1;
attribute attribute_2 : string;
attribute attribute_2 of b : signal is attr2;

attribute syn_keep : boolean;
attribute syn_keep of a : signal is true;
attribute syn_keep of b : signal is true;
begin

a <= ia; oa <= a;

b <= ib; ob <= b;

end architecture rtl;
---end-vhdl-code---------

I hope I did not not jump the gone, but it would be great if anyone
can come up with an elegant solution.
-- Amal

 

[Muzaffer Kal]

On Wed, 18 Nov 2009 00:15:29 -0800 (PST), Jonathan Bromley
<spam@oxfordbromley.plus.com> wrote:

On Nov 17, 11:08 pm, Amal <akhailt...@gmail.com> wrote:
Here is another frustrating missing feature in V2K and SV.
[...]
Basically I would like to attach an attribute
to a declaration inside a module. The attribute could vary from
instance to instance. I thought I use macro defines, but couldn't
think of a way to do it per instance.

Yes. You're not the first person to have asked about it.

I suspect that it's missing mainly because the Verilog design
community tends to be ASIC-based, and they tend to do this sort
of thing at a later stage in the design flow - not as part of
the Verilog design capture. VHDL FPGA users make heavy use of
the ability to construct attribute values programmatically, but
it's not surfaced as an issue for the dominant Verilog users.

Absolutely; when one needs something like this in an ASIC flow, one

writes usually writes a script (perl, tcl, python ...) which generates
the script in the language of the back-end tool to do the placement.

Interestingly, in a recent discussion elsewhere about "what would
you like to see in any future revision of SystemVerilog", this was
one of the issues that came up. Only a couple of days ago.

That's probably my posting as I'm doing more FPGA work these days and
this missing feature is just bugging me (not that I expect that it
would be resolved any time soon).
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[Jonathan Bromley]

On Nov 17, 11:08 pm, Amal <akhailt...@gmail.com> wrote:

Here is another frustrating missing feature in V2K and SV.
[...]
Basically I would like to attach an attribute
to a declaration inside a module. The attribute could vary from
instance to instance. I thought I use macro defines, but couldn't
think of a way to do it per instance.

Yes. You're not the first person to have asked about it.

I suspect that it's missing mainly because the Verilog design
community tends to be ASIC-based, and they tend to do this sort
of thing at a later stage in the design flow - not as part of
the Verilog design capture. VHDL FPGA users make heavy use of
the ability to construct attribute values programmatically, but
it's not surfaced as an issue for the dominant Verilog users.

Interestingly, in a recent discussion elsewhere about "what would
you like to see in any future revision of SystemVerilog", this was
one of the issues that came up. Only a couple of days ago.
--
Jonathan

 

[Amal]

On Nov 18, 3:50 am, Muzaffer Kal <k...@dspia.com> wrote:

On Wed, 18 Nov 2009 00:15:29 -0800 (PST), Jonathan Bromley





s...@oxfordbromley.plus.com> wrote:
On Nov 17, 11:08 pm, Amal <akhailt...@gmail.com> wrote:
Here is another frustrating missing feature in V2K and SV.
[...]
Basically I would like to attach an attribute
to a declaration inside a module.  The attribute could vary from
instance to instance.  I thought I use macro defines, but couldn't
think of a way to do it per instance.

Yes.  You're not the first person to have asked about it.

I suspect that it's missing mainly because the Verilog design
community tends to be ASIC-based, and they tend to do this sort
of thing at a later stage in the design flow - not as part of
the Verilog design capture. VHDL FPGA users make heavy use of
the ability to construct attribute values programmatically, but
it's not surfaced as an issue for the dominant Verilog users.

Absolutely; when one needs something like this in an ASIC flow, one
writes usually writes a script (perl, tcl, python ...) which generates
the script in the language of the back-end tool to do the placement.

Interestingly, in a recent discussion elsewhere about "what would
you like to see in any future revision of SystemVerilog", this was
one of the issues that came up.  Only a couple of days ago.

That's probably my posting as I'm doing more FPGA work these days and
this missing feature is just bugging me (not that I expect that it
would be resolved any time soon).
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Yes, it seems not many people are doing ASICs these days. I remember
a couple of years ago, there was a talk about how to even put (timing)
constraints at the RTL level. Managing scripts is sometimes
difficult, error-prone and tedious. I usually like a self-contained,
configurable design module that can be used in different projects.
Many of the back-end constraints, attributes could be placed up-front
and just propagated all the way down the tool chain.

Well, nowadays I wish we were using VHDL more, but can you think of
any way to somehow achieve this in Verilog?
-- Amal

 

[Muzaffer Kal]

On Wed, 18 Nov 2009 06:28:21 -0800 (PST), Amal <akhailtash@gmail.com>
wrote:

Well, nowadays I wish we were using VHDL more, but can you think of
any way to somehow achieve this in Verilog?

You can always embed a (perl,tcl,python etc) script in your verilog
code and pre-process it to do the text replacement you need. It should
the task of the synthesis front-end but that option is open to you if
you need it.

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[Mike Treseler]

Amal wrote:

Well, nowadays I wish we were using VHDL more, but can you think of
any way to somehow achieve this in Verilog?
-- Amal

Here's a nice verilog generator in python:
http://www.myhdl.org

-- Mike Treseler

 

On Nov 17, 5:08 pm, Amal <akhailt...@gmail.com> wrote:

Here is another frustrating missing feature in V2K and SV.  I have a
dilemma and it relates to the way attributes are defined in Verilog
200x and SystemVerilog.  Basically I would like to attach an attribute
to a declaration inside a module.  The attribute could vary from
instance to instance.  I thought I use macro defines, but couldn't
think of a way to do it per instance.

Unless I am misunderstanding something, this is easy to do.

The value of a Verilog attribute can be set to a constant expression,
which means it can be set to a parameter value. I assume this is the
same thing your VHDL version is doing with a generic.

Here is what I like to do in Verilog and be able to change attribute_1
and attribute_2 values per instance:

---start-modified-verilog-code---------

module xyx;

parameter attr1 = "value_1";
parameter attr2 = 1;

  // This
  (* keep = attr2, attribute_1 = attr1 *)
  reg a;

endmodule //:xyx
---end-verilog-code---------

You are on your own with the "comment pragmas", since those
are a tool hack that are not part of the language.

I don't know whether there is widespread support for attributes
and setting their values to arbitrary constant expressions. But
that would not be the fault of the language definition.

 

[Amal]

On Nov 21, 11:31 pm, sh...@cadence.com wrote:

On Nov 17, 5:08 pm, Amal <akhailt...@gmail.com> wrote:

Here is another frustrating missing feature in V2K and SV.  I have a
dilemma and it relates to the way attributes are defined in Verilog
200x and SystemVerilog.  Basically I would like to attach an attribute
to a declaration inside a module.  The attribute could vary from
instance to instance.  I thought I use macro defines, but couldn't
think of a way to do it per instance.

Unless I am misunderstanding something, this is easy to do.

The value of a Verilog attribute can be set to a constant expression,
which means it can be set to a parameter value.  I assume this is the
same thing your VHDL version is doing with a generic.

Here is what I like to do in Verilog and be able to change attribute_1
and attribute_2 values per instance:

---start-modified-verilog-code---------
module xyx;

parameter attr1 = "value_1";
parameter attr2 = 1;

   // This
   (* keep = attr2, attribute_1 = attr1 *)
   reg a;

 endmodule //:xyx
---end-verilog-code---------

You are on your own with the "comment pragmas", since those
are a tool hack that are not part of the language.

I don't know whether there is widespread support for attributes
and setting their values to arbitrary constant expressions.  But
that would not be the fault of the language definition.

I did not know you can assign parameters to Verilog attributes!
That's great! But can you pass the whole line between (* and *) as a
parameter as well?

I am asking because I have multiple attributes. It this case, I need
to pass all of them I guess.

Thanks. Wonderful!
-- Amal