C
comp.lang.verilog
Guest
Can't I pass array of signals (each signal having two bits) to a
module.
i tried lot on this ,is it possible in verilog.
Here is what i tried:
module traffic_controller(light[3:0],clk,reset);
//port declaration
output [1:0]light[3:0]; //I require to output 4 signal lines with each
signal having 2 bits
input clk;
input reset;
This is not working .What is the way to do this?
module.
i tried lot on this ,is it possible in verilog.
Here is what i tried:
module traffic_controller(light[3:0],clk,reset);
//port declaration
output [1:0]light[3:0]; //I require to output 4 signal lines with each
signal having 2 bits
input clk;
input reset;
This is not working .What is the way to do this?