Passing digitized data to design

[Mohammed Billoo]

Hello,

Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design.

Thanks
Mohammed

 

[Rick C]

On Tuesday, May 5, 2020 at 11:36:23 PM UTC-4, Mohammed Billoo wrote:

Hello,

Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design.

Thanks
Mohammed

Do you mean a "design" in a simulation or in an FPGA? In an FPGA I would expect your system to already be capable of sending data to it. If not, how do you plan to use the design?

In a simulation you need to have the data in a file which can be read out by a test bench and provided to the simulated FPGA by simulating the interfaces to the FPGA.

I typically spend as much effort on the test benches for my designs as I do the designs themselves.

--

Rick C.

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[Mohammed Billoo]

Sorry, yes I meant in simulation. I imagine there are many good resources online that show how to set up a testbench for this purpose in Vivado.

Thanks

On Wednesday, May 6, 2020 at 3:07:32 AM UTC-4, Rick C wrote:

On Tuesday, May 5, 2020 at 11:36:23 PM UTC-4, Mohammed Billoo wrote:
Hello,

Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design.

Thanks
Mohammed

Do you mean a "design" in a simulation or in an FPGA? In an FPGA I would expect your system to already be capable of sending data to it. If not, how do you plan to use the design?

In a simulation you need to have the data in a file which can be read out by a test bench and provided to the simulated FPGA by simulating the interfaces to the FPGA.

I typically spend as much effort on the test benches for my designs as I do the designs themselves.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Wednesday, May 6, 2020 at 9:54:45 AM UTC-4, Mohammed Billoo wrote:
> Sorry, yes I meant in simulation. I imagine there are many good resources online that show how to set up a testbench for this purpose in Vivado.

I assume Vivado is a simulation tool? That is agnostic to the issue. You simply need to learn how to use the HDL you are using. Once you know that you can write the test bench to operate the other side of the interface from the FPGA.

What sort of interfaces do you have?

--

Rick C.

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[Mohammed Billoo]

On Wednesday, May 6, 2020 at 11:31:20 AM UTC-4, Rick C wrote:

On Wednesday, May 6, 2020 at 9:54:45 AM UTC-4, Mohammed Billoo wrote:
Sorry, yes I meant in simulation. I imagine there are many good resources online that show how to set up a testbench for this purpose in Vivado.

I assume Vivado is a simulation tool? That is agnostic to the issue. You simply need to learn how to use the HDL you are using. Once you know that you can write the test bench to operate the other side of the interface from the FPGA.

What sort of interfaces do you have?

It looks like there is non-synthesizable VHDL that will allow me to read in a file, convert from unsigned to a std logic vector and pass it to my module as a DUT.

--

Rick C.

+ Get 1,000 miles of free Supercharging
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[Rick C]

On Wednesday, May 6, 2020 at 6:50:44 PM UTC-4, Mohammed Billoo wrote:

On Wednesday, May 6, 2020 at 11:31:20 AM UTC-4, Rick C wrote:
On Wednesday, May 6, 2020 at 9:54:45 AM UTC-4, Mohammed Billoo wrote:
Sorry, yes I meant in simulation. I imagine there are many good resources online that show how to set up a testbench for this purpose in Vivado.

I assume Vivado is a simulation tool? That is agnostic to the issue. You simply need to learn how to use the HDL you are using. Once you know that you can write the test bench to operate the other side of the interface from the FPGA.

What sort of interfaces do you have?

It looks like there is non-synthesizable VHDL that will allow me to read in a file, convert from unsigned to a std logic vector and pass it to my module as a DUT.

Not sure what you mean by "there is", but yes, your test bench does not need to be synthesized since it is not going to be part of the design compiled for your FPGA. It will be up to you to write it and make it work like the environment your FPGA will work in.

There were times I even simulated analog hardware like an RC filter to process the output of a single bit DAC and produce an "analog" output. The simulator allows plotting the value of an integer as a waveform reproducing my output signal like an oscilloscope. The test bench could sample that analog signal, create a sound file which could then be played back outside the simulation.

--

Rick C.

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