passing arrays to modules

[Robert Finch]

Hi,

Is it possible to pass an array to a module in Verilog ? If so How ? I tried
this:

module arrayTest(s, a, o);
input [2:0] s;
input [3:0] a [4:0]; // this line cause the synthesizer to
croak with an error 'expecting ; not [ '
output [3:0] o;

assign o = a;

endmodule


Thanks,
Rob

 

[John McBride]

John McBride wrote:

John McBride wrote:

Robert Finch wrote:

Hi,

Is it possible to pass an array to a module in Verilog ? If so How ?
I tried this:

module arrayTest(s, a, o);
input [2:0] s;
input [3:0] a [4:0]; // this line cause the synthesizer to
croak with an error 'expecting ; not [ '
output [3:0] o;

assign o = a;

endmodule


Thanks,
Rob


I don't think it is possible, for example I had an array of 4 x 4 bit
BCD numbers, I ended up just passing a 16 bit vector and then just
splitting it up again within the module:

---
input bcd_vector [15:0];

reg [3:0] bcd_char [3:0];
integer i;


always @(bcd_vector)
begin: split_up_vector

for(i=0;i<4;i=i+1)
begin
bcd_char <= bcd_vector[(4*i +4)4*i)];
end
end

---

Then you gotta construct the vector when passing it in.

I think though it kinda defeats the purpose fo the array in this
context - which is to allow a flexible interface to your module.
Though, if you parameterise the above code you would make it quite
flexible.

I'll check the verilog XL manual, as I never really looked into it, I
just used vectors.

John



OK you can only pass in a flat array, so you have two options:


1) pass in flat array

module array(a);
input [M:0] a;

2) pass in vector

module vector(a);
input a [N:0];


BUT not

module mixed(a);
input [M:0] a [N:0];

sorry!
check out this person's approach:

http://zoo.cs.yale.edu/classes/cs490/98-99a/harb/writeup.html

search for the line:
The above module takes as input the 8? 32-bit flat array a, and outputs
the 32-bit array sum. ...