pass value from system verilog to VHDL (std_logic_vector)

[sundar]

Hi,
In my VHDL DUT I have a generic declared as std_logic_vector as below
generic_name : std_logic_vector := "0100000000";

My verification environment is in System Verilog where I need to pass
a value to this generic during mapping it in System Verilog

dut
#(
..generic_name (),
)
....
I cudnt able to pass any value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

Please let me know your thoughts.

Thanks,
Sundar
Note: I had a workaround by leaving the dut mapping as blank and
passing value during vsim like
-g/tb/dut_0/generic_name=10'b0100000000

 

[Jonathan Bromley]

On Mon, 12 Nov 2007 11:00:22 -0000, sundar <sundar.ece@gmail.com>
wrote:

Hi,
In my VHDL DUT I have a generic declared as std_logic_vector as below
generic_name : std_logic_vector := "0100000000";

My verification environment is in System Verilog where I need to pass
a value to this generic during mapping it in System Verilog

dut
#(
.generic_name (),
)
...
I cudnt able to pass any value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

Please let me know your thoughts.

This is a tool-specific problem (there is no formal standard for
cross-language working) so you should perhaps take a closer look
at the Mentor documentation. However, it's worth noting that
parameters in (System)Verilog are integers by default, so it
might be a good idea to put your VHDL DUT in a simple VHDL
wrapper that maps the generic from integer to s-l-v:

entity wrapper is
generic (vlog_generic_name: integer := 256);
port (.....); -- same port list as your DUT
end;
architecture fake of wrapper is
begin
VHDL_DUT: DUT
generic map (generic_name =>
std_logic_vector(to_unsigned(vlog_generic_name, 10))
)
port map (clock => clock, .....);
end;

This same wrapper could usefully do other Verilog-friendly
things such as renaming ports to avoid conflict with
Verilog keywords, exploding complicated structured ports
in VHDL to collections of simpler ports for Verilog,
and so forth.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[sundar]

Hi Jonathan,
Thanks for your inputs. Similar ideas were also shared in AVM user
group.
I tried passing integer and convert it in wrapper and found it is
working.
Thanks again,
Sundar
On Nov 22, 2:32 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Mon, 12 Nov 2007 11:00:22 -0000, sundar <sundar....@gmail.com
wrote:



Hi,
In my VHDL DUT I have a generic declared as std_logic_vector as below
generic_name : std_logic_vector := "0100000000";

My verification environment is in System Verilog where I need topass
a value to this generic during mapping it in System Verilog

dut
#(
.generic_name (),
)
...
I cudnt able topassany value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

Please let me know your thoughts.

This is a tool-specific problem (there is no formal standard for
cross-language working) so you should perhaps take a closer look
at the Mentor documentation. However, it's worth noting that
parameters in (System)Verilog are integers by default, so it
might be a good idea to put your VHDL DUT in a simple VHDL
wrapper that maps the generic from integer to s-l-v:

entity wrapper is
generic (vlog_generic_name: integer := 256);
port (.....); -- same port list as your DUT
end;
architecture fake of wrapper is
begin
VHDL_DUT: DUT
generic map (generic_name =
std_logic_vector(to_unsigned(vlog_generic_name, 10))
)
port map (clock => clock, .....);
end;

This same wrapper could usefully do other Verilog-friendly
things such as renaming ports to avoid conflict with
Verilog keywords, exploding complicated structured ports
in VHDL to collections of simpler ports for Verilog,
and so forth.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.