Partial Reconfig - PAR fails with ISE 6.1 SP3

I

Ian

Guest
I have a simple partial reconfig design. Under ISE6 SP2 it is only
routable using fpga editor, command line PAR fails with the message
'abnormal program termination'. Not a big problem as fpga editor does
the job!

But after installing SP3, command line PAR and fpga editor fail
reporting the design is unroutable. The problem is confirmed as being
SP3 as I have now uninstalled it and the design routes OK.

If anyone is having similar problems routing a design you may want to
do the same.

I would also like to thank Kamal Patel at Xilinx for his help and for
creating a Spartan 2 bus macro, amazing service!! Cheers :)
 
Hello, Ian:

I saw you mentioned the Spartan-2 bus macro, could you exchange it with me?
I am willing to trade
for it with a complete partial reconfig design (vertex-2)...that was the
tutorial I did, though...My email
address is kelvin8157@hotmail.com...

Best Regards,
Kelvin


"Ian" <tau14@sussex.ac.uk> wrote in message
news:63c49b7e.0402160714.4a20dd45@posting.google.com...
I have a simple partial reconfig design. Under ISE6 SP2 it is only
routable using fpga editor, command line PAR fails with the message
'abnormal program termination'. Not a big problem as fpga editor does
the job!

But after installing SP3, command line PAR and fpga editor fail
reporting the design is unroutable. The problem is confirmed as being
SP3 as I have now uninstalled it and the design routes OK.

If anyone is having similar problems routing a design you may want to
do the same.

I would also like to thank Kamal Patel at Xilinx for his help and for
creating a Spartan 2 bus macro, amazing service!! Cheers :)
Click to expand...
 
Hi Ian,

Ian wrote:
I have a simple partial reconfig design. Under ISE6 SP2 it is only
routable using fpga editor, command line PAR fails with the message
'abnormal program termination'. Not a big problem as fpga editor does
the job!

But after installing SP3, command line PAR and fpga editor fail
reporting the design is unroutable. The problem is confirmed as being
SP3 as I have now uninstalled it and the design routes OK.

If anyone is having similar problems routing a design you may want to
do the same.
Click to expand...
I don't know if you saw the thread about this a few days ago, I had some
similar inexplicable problems with the tools producing invalid NCDs,
that would crash the FPGAeditor and bitgen tools.

The bottom line seems to be that there are still a lot of issues to be
worked out! I'm sorry I don't have any concrete suggestions for your
problem, but it does make me wonder...

Would there be interest in a partial reconfiguration research mailing
list? Or, is there already such a thing?

Our department has a list-server configured and ready for use (I
currently run the microblaze uclinux list on it). I'd be happy to setup
and maintain such a list, if there was interest.

Regards,

John
 
Kelvin, bus macro sent via Email. Anybody else need this part just ask!!

John, I'm glad it's not just me!


Also, thanks to John, the partial reconfig list is now active at

http://www.itee.uq.edu.au/~listarch/partial-reconfig/

just one thought however, does it have to be restriced to Xilinx devices??

Cheers All,
Ian.
 
Ian wrote:
Also, thanks to John, the partial reconfig list is now active at

http://www.itee.uq.edu.au/~listarch/partial-reconfig/
Click to expand...
Thanks for the advertising Ian :) Anyone wanting to join can send an
email to majordomo@itee.uq.edu.au, with the *body text*

subscribe partial-reconfig

just one thought however, does it have to be restriced to Xilinx
devices??
Click to expand...

Not at all - I just wonder how much of the detailed implementation /
tool flow discussion would be relevant between brands A & X.

I'm happy to broaden the charter to partial and dynamic reconfiguration
generally.

Regards,

John
 
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