Partial Aggregate Assignment

[Paul B]

Hi all,

I'm trying to write a tight piece of code which will pick all the individual
signals out of an slv as I need them. So I have a vector whos bits are not
all used.

What I was thinking was:

(a, b, , c, , d, e, f) <= SLV_SIGNAL;


or

(a, b, open, c, open, d, e, f) <= SLV_SIGNAL;


where

signal a,b,c,d,e,f : std_logic;

signal SLV_SIGNAL : std_logic_vector;

Is there any compact way of doing this instead of writing:

a <= SLV_SIGNAL(7);

b <= SLV_SIGNAL(6);

c <= SLV_SIGNAL(4);

d <= SLV_SIGNAL(2);

e <= SLV_SIGNAL(1);

f <= SLV_SIGNAL(0);

TIA!

Paul

 

[Mike Treseler]

Paul B wrote:

What I was thinking was:
(a, b, , c, , d, e, f) <= SLV_SIGNAL;

http://groups-beta.google.com/groups/search?q=15%3A27%3A54+entity+aggregate

-- Mike Treseler

 

[Paul B]

Hmm yes, but I need a way to take only a few of the signals from the source,
hence the commas marking unused elements. At the moment I have them going to
dummy signals.

Mike Treseler <mike_treseler@comcast.net> wrote:

Paul B wrote:tm> What I was thinking was:4> (a, b, , c, , d, e, f) <=
SLV_SIGNAL;00http://groups-beta.google.com/groups/search?q=15%3A27%3A54+entity+aggregatem

-- Mike Treseler

 

[Mike Treseler]

Paul B wrote:

Hmm yes, but I need a way to take only a few of the signals from the source,
hence the commas marking unused elements. At the moment I have them going to
dummy signals.

If "SLV_SIGNAL" is an input value to your process,
and if these port/signal bits are already in scope,
I would just reference the bits I need and ignore the rest.
If the intent is to identify the bit, I would declare index constants:
constant ready : natural := 2; -- status bit location
-- ...
if SLV_SIGNAL(ready) = '1' then
-- ...

-- Mike Treseler

 

[Paul Uiterlinden]

Paul B wrote:

signal a,b,c,d,e,f : std_logic;

signal SLV_SIGNAL : std_logic_vector;

Is there any compact way of doing this instead of writing:

a <= SLV_SIGNAL(7);

b <= SLV_SIGNAL(6);

c <= SLV_SIGNAL(4);

d <= SLV_SIGNAL(2);

e <= SLV_SIGNAL(1);

f <= SLV_SIGNAL(0);

Yes: use aliases:

signal SLV_SIGNAL : std_logic_vector;
alias a: std_logic is SLV_SIGNAL(7);
alias b: std_logic is SLV_SIGNAL(6);
etcetera

Now you can not only read a, b,..., but also assign to them:
a <= '1';

This is equivalent to:
SLV_SIGNAL(7) <= '1';

--
Paul.
www.aimcom.nl
email address: switch x and s