Part Selects in verilog

V

Vishu

Guest
Hello All,

I have a question on part selects that hopefully someone can help me
with. I am trying to implement swapping and shifting of a 32-bit
address bus to a 24-bit address bus. I am using the Xilinx ISE
synthesis tool.

I am familiar with the right way to implement this in VHDL but I am not
very proficient in Verliog to know what the equivalent syntax would
look like.


-- VHDL code that works --
MAP_ADDR(23 DOWNTO 0) <= ADDR(7 TO 30) WHEN (lsize = '1')
ELSE ADDR(8 TO 31);
---------------------------------------------------------



//** VERILOG CODE RESULTS IN ERROR**
input [31:6] ADDR;
output [23:0] MAP_ADDR;
wire [1:0] lsize;

assign MAP_ADDR[23:0] = (lsize == 1'b1) ? ADDR[7:30] : ADDR[8:31];
//****************************************************************

Error Message:
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
ERROR:HDLCompilers:185 - lbaddrgen.v line 44 Illegal right hand side of
continuous assign



Any input is deeply appreciated.

Best Regards,
Vishu
 
try,
assign MAP_ADDR[23:0] = (lsize == 1'b1) ? ADDR[30:7] : ADDR[31:8];

enjoy
 
Vishu wrote:
...
-- VHDL code that works --
MAP_ADDR(23 DOWNTO 0) <= ADDR(7 TO 30) WHEN (lsize = '1')
ELSE ADDR(8 TO 31);
---------------------------------------------------------



//** VERILOG CODE RESULTS IN ERROR**
input [31:6] ADDR;
output [23:0] MAP_ADDR;
wire [1:0] lsize;
==========^^^^^

assign MAP_ADDR[23:0] = (lsize == 1'b1) ? ADDR[7:30] : ADDR[8:31];
===================================^^^==========^^^^^^=======^^^^^^
//****************************************************************

Error Message:
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
---------------------^^^^^^^^^^^^
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
---------------------^^^^^^^^^^^^
ERROR:HDLCompilers:185 - lbaddrgen.v line 44 Illegal right hand side of
continuous assign

...
Click to expand...
based on items marked ---^^^^ above, this should work:

assign MAP_ADDR[23:0] = (lsize == 2'b1) ? ADDR[30:7] : ADDR[31:8];
 
Thanks for the replies...
stud_lang...@yahoo: I did try your suggestion and the complier does
not complain. But my intention is to assign ADDR[7] to MAP_ADDR[23]
and ADDR[31] to MAP_ADDR[0].

The use of "downto" keyword allows me to assign it in this manner in
the case of VHDL. I was wondering if this kind of assignment is
possible in verilog or if it is the synthesis tool that is complaining.

John Rible: Sorry about the error. The declaration should read "wire
lsize".
 
Verilog allows the declaration of wire ranges in either upward or
downward fashion. The trouble is, all references have to follow that
same order, whether non-indexed assignments, part selects, whatever.

The VHDL would work almost directly if you ADDR were declared backwards
from the "typical" declaration.

..
..
..
input [0:31] ADDR;
..
..
..
wire [23:0] MAP_ADDR;
..
..
..
assign MAP_ADDR[23:0] = (lsize == 1'b1) ? ADDR[7:30] : ADDR[8:31];

The declaration order would allow this to compile correctly. If you
need to refer to the address is a "DOWNTO" fashion elsewhere, the "UPTO"
form of the ADDR declaration wouldn't work. I've used a manual
bit-swizzle many times in my own code where I have to declare each bit
(all 32 in your case) as individual bits to reassign an "UPTO" vector to
a "DOWNTO" reference such as:

input [31:0] ADDR;
..
..
..
wire [0:31] AddrSwiz
= { ADDR[31],ADDR[30],ADDR[29],ADDR[28]
,ADDR[27],ADDR[26],ADDR[25],ADDR[24]
,ADDR[23],ADDR[22],ADDR[21],ADDR[20]
,ADDR[19],ADDR[18],ADDR[17],ADDR[16]
,ADDR[15],ADDR[14],ADDR[13],ADDR[12]
,ADDR[11],ADDR[10],ADDR[ 9],ADDR[ 8]
,ADDR[ 7],ADDR[ 6],ADDR[ 5],ADDR[ 4]
,ADDR[ 3],ADDR[ 2],ADDR[ 1],ADDR[ 0] };


Verilog misses on a few "convenient" points that System Verilog seems to
widely address though I'm not certain if the UPTO/DOWNTO are easily
swapped in the up and coming standard.



Vishu wrote:

Hello All,

I have a question on part selects that hopefully someone can help me
with. I am trying to implement swapping and shifting of a 32-bit
address bus to a 24-bit address bus. I am using the Xilinx ISE
synthesis tool.

I am familiar with the right way to implement this in VHDL but I am not
very proficient in Verliog to know what the equivalent syntax would
look like.


-- VHDL code that works --
MAP_ADDR(23 DOWNTO 0) <= ADDR(7 TO 30) WHEN (lsize = '1')
ELSE ADDR(8 TO 31);
---------------------------------------------------------



//** VERILOG CODE RESULTS IN ERROR**
input [31:6] ADDR;
output [23:0] MAP_ADDR;
wire [1:0] lsize;

assign MAP_ADDR[23:0] = (lsize == 1'b1) ? ADDR[7:30] : ADDR[8:31];
//****************************************************************

Error Message:
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
ERROR:HDLCompilers:191 - lbaddrgen.v line 44 Indices in part-select of
vector wire 'ADDR' are reversed
ERROR:HDLCompilers:185 - lbaddrgen.v line 44 Illegal right hand side of
continuous assign



Any input is deeply appreciated.

Best Regards,
Vishu
Click to expand...
 
John_H,

Thanks for the AddrSwiz tip. I finally got it to work.

Thanks to everyone who replied as well.

Regards,
Vishu
 
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