part select on literals / macros?

[unfrostedpoptart]

Question for the group:

In many header files I've used, I've defined constants (typically
addresses) as parameters:
localparam [31:0] ADDRESS_A = 32'h1000_0004;

In case statements based on a subset of the parameter I am able to use
a part select ( ADDRESS_A[7:0]). However, in some other code I need
to import, the engineer is using macros:
`define ADDRESS_A 32'h1000_0004

But it's not legal to do a part-select on a literal
( `ADDRESS_A[7:0]). A workaround is to assign it first to a dummy
wire, but I was hoping for something more elegant. Any suggestions?
Why doesn't Verilog support this?

Thanks,

David

 

On Oct 13, 6:47 pm, unfrostedpoptart wrote:

it's not legal to do a part-select on a literal
( `ADDRESS_A[7:0]). A workaround is to assign it first to a dummy
wire, but I was hoping for something more elegant. Any suggestions?
Why doesn't Verilog support this?

Because it would have some nasty implications elsewhere
in the language. If you allow part-select on any expression,
what happens when you try to do

a[4:7][1:0]

?? Do you really mean "a[6:7]" (the two LSBs of a[4:7])
or are you trying to slice a 2-dimensional array?

So it's not quite as easy as it might look. However, the
new unified Verilog/SystemVerilog standard, 1800-2009, is
expected to have the ability to part-select or subscript
a concatenation; so your example will then be workable as

assign a = {`MY_MACRO}[3:0]

and then, whatever MY_MACRO might be - a literal, an
expression, a variable, a part-select, whatever - you
will get the four LSBs of it. Unlike regular concatenation,
this form will not be allowed on the left side of an
assignment.

1800-2009 includes a number of such enhancements that will
be widely useful to Verilog programmers even if they don't
wish to adopt SystemVerilog. Badger your tool vendors for
these features as soon as the ink's dry on the standard
some time next year:

- text I/O improvements: %p formatter, and numeric field
widths in format strings like %3d
- the ability to define parameters without a default value,
so that it becomes mandatory to override them on
instantiation:
module M #(parameter P); ... endmodule
....
M m(); // illegal, P is not overridden
M #(.P(42)) m1(); // OK, P given a value
- localparams in parameter port lists so that you can
force your parameters to have appropriate relationships:
module Decode #(parameter bits_in = 3,
localparam bits_out = 1<<bits_in)
(input [bits_in-1:0] A,
output [bits_out-1:0] Y);
assign Y = 1 << A;
endmodule
...
Decode #(4) decode4to16(a4, y16); //ok, bits_out=16
Decode #(5,25) decode5to32 (...); //illegal, can't override
bits_out
- default values for module input ports left unconnected
- `__FILE__ and `__LINE__ predefined macros for better error
reporting

This isn't SystemVerilog rocket science; it's good simple stuff
that will make life easier and better for all Verilog users.
Respect to the SystemVerilog Basic Committee for pushing these
changes through when there were other, sexier SystemVerilog things
to do as well.
--
Jonathan Bromley