part-select in Xilinx ISE 6.1i

[duststar]

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.

////////////////////////////////////////////////////////////////
module ttt(clk, Din, Dout);
input clk;
input [127:0] Din;
output [127:0] Dout;
reg [127:0] Dout;
reg [7:0] temp [0:15];
integer i;
always@(posedge clk)
begin
for(i=0;i<=15;i=i+1)
begin
temp=Din[(127-8*i) -:8]; //line 14
end
Dout={temp[0],temp[1],temp[2],temp[3],
temp[4],temp[5],temp[6],temp[7],
temp[8],temp[9],temp[10],temp[11],
temp[12],temp[13],temp[14],temp[15]};
end
endmodule
////////////////////////////////////////////////////////////////

 

[hmmmm]

I just tried Xilinx Webpack(ISE) 6.2i (with SP3) -- same problem.
Apparently, XST (Xilinx Synthesis Technology) doesn't yet support
that Verilog-2001 syntax.

The XST Verilog preprocessor still doesn't support Macro-expressions,
either.

`define MAXIMUM2 ( x , y ) ( (x)> ? (x) : )

....

parameter COMMON_BUS_WIDTH = `MAXIMUM2( OUT_A, IN_B );

Steven Sharp wrote:

g9102025@mail.ttu.edu.tw (duststar) wrote in message news:<88809cfd.0406181417.250ca130@posting.google.com>...

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.


Your code works fine in NC-Verilog, so this must be an issue with XST.
Perhaps they require a command-line option to enable Verilog-2001
features. Or perhaps they support +: but not -:. Or perhaps they
don't like something about the expression you are using for the
starting bit position.