Parser to convert a state machine written in VHDL to .dot fo

[reuven]

Hi,

Does anyone know of a parser that can convert a state machine written
in VHDL to the .dot format ?

 

[Mike Treseler]

reuven wrote:

Does anyone know of a parser that can convert a state machine written
in VHDL to the .dot format ?

Might be an interesting project.
However, the quartus state machine viewer
has already solved this problem.
It picks state machines out of vhdl or verilog
code and can print them like this:

http://home.comcast.net/~mike_treseler/pseudo_states.pdf

-- Mike Treseler