C
camelot
Guest
Hello everybody,
I've a doubt about parasitic extraction. I'm using an old cmos
technology developed in 4.3.4 opus environment. Well, if I extract
parasitic cap devices (with lpe module) over a metal line, I often
obtain capacitor linked to the net of the metal and to a generic node I
presume could be the substrate (??). Well, my question is, as I put in
the layout a substrate contact ptap (that should take p-) that have a
pin on it, while the node of parasitic capacitance that presumably are
connected to substrate are not automatically connected to that one?
Camelot
I've a doubt about parasitic extraction. I'm using an old cmos
technology developed in 4.3.4 opus environment. Well, if I extract
parasitic cap devices (with lpe module) over a metal line, I often
obtain capacitor linked to the net of the metal and to a generic node I
presume could be the substrate (??). Well, my question is, as I put in
the layout a substrate contact ptap (that should take p-) that have a
pin on it, while the node of parasitic capacitance that presumably are
connected to substrate are not automatically connected to that one?
Camelot