Parametrized IO ports

[blakaxe@gmail.com]

I have a parametrized I/O pin in my module
I want my module declaration in the following format.

EXAMPLE:

module abcd
(
input [X-1:0] data
);

parameter X = .....;


But the parameter is defined after it is used, and i get an error.
Where can I declare the parameter?

I get an error if parameter is declared before the module too.

Thanks

 

[Jonathan Bromley]

On Fri, 18 Jul 2008 06:16:25 -0700 (PDT), "blakaxe@gmail.com"
<blakaxe@gmail.com> wrote:

module abcd
(
input [X-1:0] data
);

parameter X = .....;

Verilog-2001 fixed this...

module abcd
#(parameter X = ...)
(input [X-1:0] data, ...);

And now you can override the parameter as normal:

module efgh;

abcd #(.X(1234)) abcd_instance(.data(...), ...);

One day I might understand why it took nearly twenty years
for Verilog to decide that this was a good idea.....
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Muzaffer Kal]

On Fri, 18 Jul 2008 06:16:25 -0700 (PDT), "blakaxe@gmail.com"
<blakaxe@gmail.com> wrote:

I have a parametrized I/O pin in my module
I want my module declaration in the following format.

EXAMPLE:

module abcd
(
input [X-1:0] data
);

parameter X = .....;


But the parameter is defined after it is used, and i get an error.
Where can I declare the parameter?

I get an error if parameter is declared before the module too.

Thanks

You can put the parameter declaration before the port list ie:

module abcd
#(parameter X = .....)
(
input [X-1:0] data
);

 

[Kevin Neilson]

Jonathan Bromley wrote:
abcd #(.X(1234)) abcd_instance(.data(...), ...);

One day I might understand why it took nearly twenty years
for Verilog to decide that this was a good idea.....

I also wish they had decided to put in unconstrained port sizes. Then
you wouldn't need the parameter at all. Maybe in a few more years...
-Kevin

 

[gabor]

On Jul 18, 9:16 am, "blak...@gmail.com" <blak...@gmail.com> wrote:

I have a parametrized I/O pin in my module
I want my module declaration in the following format.

EXAMPLE:

module abcd
(
input [X-1:0] data
);

parameter X = .....;

But the parameter is defined after it is used, and i get an error.
Where can I declare the parameter?

I get an error if parameter is declared before the module too.

Thanks

You could use the old Verilog '95 port convention:

module abcd
(
data
);

parameter X = .....;
input [X-1:0] data;

or if you don't need to modify the parameter from the instantiating
code you could use a macro instead like:

`define X ......

module abcd
(
input [`X-1:0] data
);

But that won't work if you have multiple instances with different X
values.

 

[blakaxe@gmail.com]

Thanks Guys