parametrizable delays

[tullio]

I need to write a behavioral code where I can delay various signals by
an arbitrary number of clocks (up to a few hundreds cycles).
Surprisingly i don't find any nice Verilog synthax for that.
The only solution I came up with is to model a *big* multiplexer,
where each data input is a delayed version of the signal.

Any smarter way ?

Tullio

 

[tullio]

On Jan 15, 3:21 pm, tullio <tullio.gra...@gmail.com> wrote:

I need to write a behavioral code where I can delay various signals by
an arbitrary number of clocks (up to a few hundreds cycles).
Surprisingly i don't find any nice Verilog synthax for that.
The only solution I came up with is to model a *big* multiplexer,
where each data input is a delayed version of the signal.

Any smarter way ?

   Tullio

I reply to myself as i found the answer to my question on this post:
http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/d423d481b8d3b99a
from Jonathan Bromley

Anyway reposting it with a more appropriate subject is probably good.

I also simulated it with Xilinx simulator (ISIM) and it works fine !

Tullio

 

[Przemek]

Ok, my take:
parametrizable, synthesizable, design with registered output and
coding style allowing efficient automatic clock gating insertion:


`include "my_defines.v"

module my_delay (
clk,
// data enable
wr_en,
// data in
data_in,
// settings
reg_delay,
// data out
data_out
);

// Global parameters
parameter DATA_BITWIDTH = 0;
parameter DELAY_MAX_LEN = 0; // actual delay len - determines length
of data shift register

// Local parameters
parameter DATA_MSB = DATA_BITWIDTH-1;
parameter DELAY_MAX_BITWIDTH = `CLOG2(DELAY_MAX_LEN+1); // bin log of
actual delay

//=========================================input clk;
input wr_en;

input [DATA_MSB:0] data_in;
input [DELAY_MAX_BITWIDTH-1:0] reg_delay;

output [DATA_MSB:0] data_out;

//====================// generate data enable

// data_en
parameter DATA_EN_WIDTH = (1<<DELAY_MAX_BITWIDTH); // power of two
resulting form bin log of actual delay (>= actual delay width)

// radius or (set unused radius data to 111 - max)
wire [DATA_EN_WIDTH-1:0] data_en;

my_1_in_n
#(
..DATA_BITWIDTH(DELAY_MAX_BITWIDTH)
)
iee_1_in_n_radius_data_en1
(
..data_in(reg_delay),
..data_out(data_en)
);

//========================================// delay register
reg [DATA_MSB:0] data_p_in_reg[DELAY_MAX_LEN-1:0];

generate
genvar i;

for(i=0;i<DELAY_MAX_LEN-1;i=i+1) begin: data_in_reg_gen

always @(posedge clk)
if(wr_en && data_en) begin
if(data_en[i+1])
data_p_in_reg <= data_p_in_reg[i+1];
else
data_p_in_reg <= data_in;
end
end
endgenerate

always @(posedge clk)
if(wr_en && data_en[DELAY_MAX_LEN-1])
data_p_in_reg[DELAY_MAX_LEN-1] <= data_in;

assign data_out = data_p_in_reg[0];
endmodule



// Temperature scale coder (bin -> temp scale)
// 0 = 0000
// 1 => 0001
// 2 => 0011
// 3 => 0111
//
module my_1_in_n (
data_in,
data_out
);

parameter DATA_BITWIDTH = 10;

// local param
parameter DATA_OUT_BITWIDTH = (1<<DATA_BITWIDTH);

input [DATA_BITWIDTH-1:0] data_in;
output [DATA_OUT_BITWIDTH-1:0] data_out;

//============reg [DATA_OUT_BITWIDTH-1:0] data_out;

generate
genvar i;

for(i=0;i<DATA_OUT_BITWIDTH;i=i+1) begin: data_out_gen
always @*
data_out = (data_in > i);
end
endgenerate
endmodule


my_defines.v:

// CEILING(LOG2)
// Return minimum width of binary number able to represent specified
number of values/states
// e.g. number of states = 2 bin width = 1 (0,1)
// for SystemVerilog deficient env.

`define CLOG2 ( n <= 2 ? 1 : \
( n <= (1<<2 ) ? 2 : \
( n <= (1<<3 ) ? 3 : \
( n <= (1<<4 ) ? 4 : \
( n <= (1<<5 ) ? 5 : \
( n <= (1<<6 ) ? 6 : \
( n <= (1<<7 ) ? 7 : \
( n <= (1<<8 ) ? 8 : \
( n <= (1<<9 ) ? 9 : \
( n <= (1<<10) ? 10 : \
( n <= (1<<11) ? 11 : \
( n <= (1<<12) ? 12 : \
( n <= (1<<13) ? 13 : \
( n <= (1<<14) ? 14 : \
( n <= (1<<15) ? 15 : \
( n <= (1<<16) ? 16 : \
( n <= (1<<17) ? 17 : \
( n <= (1<<18) ? 18 : \
( n <= (1<<19) ? 19 : \
( n <= (1<<20) ? 20 : \
( n <= (1<<21) ? 21 : \
( n <= (1<<22) ? 22 : \
( n <= (1<<23) ? 23 : \
( n <= (1<<24) ? 24 : \
( n <= (1<<25) ? 25 : \
( n <= (1<<26) ? 26 : \
( n <= (1<<27) ? 27 : \
( n <= (1<<28) ? 28 : \
( n <= (1<<29) ? 29 : \
( n <= (1<<30) ? 30 : \
( n <= (1<<31) ? 31 : \
( n <= (1<<32) ? 32 : \
( n <= (1<<33) ? 33 : \
( n <= (1<<34) ? 34 : \
( n <= (1<<35) ? 35 : \
( n <= (1<<36) ? 36 : \
( n <= (1<<37) ? 37 : \
( n <= (1<<38) ? 38 : \
( n <= (1<<39) ? 39 : \
( n <= (1<<40) ? 40 : \
( n <= (1<<41) ? 41 : \
( n <= (1<<42) ? 42 : \
( n <= (1<<43) ? 43 : \
( n <= (1<<44) ? 44 : \
( n <= (1<<45) ? 45 : \
( n <= (1<<46) ? 46 : \
( n <= (1<<47) ? 47 : \
( n <= (1<<48) ? 48 : \
( n <= (1<<49) ? 49 : \
50 )))))))))))))))))))))))))))))))))))))))))))))))))




On Jan 15, 6:35 am, tullio <tullio.gra...@gmail.com> wrote:

On Jan 15, 3:21 pm, tullio <tullio.gra...@gmail.com> wrote:

I need to write a behavioral code where I can delay various signals by
an arbitrary number of clocks (up to a few hundreds cycles).
Surprisingly i don't find any nice Verilog synthax for that.
The only solution I came up with is to model a *big* multiplexer,
where each data input is a delayed version of the signal.

Any smarter way ?

   Tullio

I reply to myself as i found the answer to my question on this post:http://groups.google.com/group/comp.lang.verilog/browse_thread/thread...
from  Jonathan Bromley

Anyway reposting it with a more appropriate subject is probably good.

I also simulated it with Xilinx simulator (ISIM) and it works fine !

 Tullio