parameterizing number of ports?

[Pasacco]

Hi

I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
entity with parameterized ports.
I am trying generic statement, yet with no success --:
Could someone give some idea?
Thankyou


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-- 4-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C,D: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B,C,D)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= D;
end case;
end process SEL_PROCESS;
end RTL;
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-- 2-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when "0" => SIG <= A;
when others => SIG <= B;
end case;
end process SEL_PROCESS;
end RTL;
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