Parameterized Verilog and long-module names in Ambit/PKS

[mwrew]

Some of our Verilog-RTL code contains 'parameterized instantiation.'

module adder(x,y,z)
parameter DW = 8;
input signed [DW-1:0] x, y;
output signed [DW:0] z;

assign z = x + y;
endmodule

module sop ...

parameter T1W = 12;
parameter T2W = T1W+1;

wire signed [T1W-1:0] t1_x, t1_y;
wire signed [T1W:0] t1_z;

wire signed [T2W-1:0] t2_x, t2_y;
wire signed [T2W:0] t2_z;

adder #( .DW(T1W) ) adder_T1(
.x(t1_x), .y(t1_y), .z(t1_y) );

adder #( .DW(T2W) ) adder_T2(
.x(t2_x), .y(t2_y), .z(t2_y) );

....

After synthesizing this in Ambit, the gate-netlist contains some
ridiculously long module names...

module adder_T1_T1W_12_T2W_13_...( );

The problem is some of our backend tools (Silicon Ensemble) don't
like long identifiers. Design Compiler has a nice compiler switch
for disabling the template-name insertion (when synthesizing
parameterized Verilog-RTL.)

Does PKS/Ambit have a similar switch? Or do users have to manually
rename the modules by hand?