L
leon
Guest
Hi,
I would like to have parameterized functions in packages. These
functions need to be used in different modules which will be
instantiated with different parameter sizes. System Verilog treats
parameters in packages as localparam and cannot be overriden. Is there
another mechanism to do this so the code is synthesizable.
Noel
I would like to have parameterized functions in packages. These
functions need to be used in different modules which will be
instantiated with different parameter sizes. System Verilog treats
parameters in packages as localparam and cannot be overriden. Is there
another mechanism to do this so the code is synthesizable.
Noel