Parameterized Comparator Code

Guest
Hello:

I am trying to write some code for a comparator. Is it possible to
write the code as so

module comparator(A_lt_B, A_gt_B, A_eq_zero, B_eq_zero, A, B);

parameter D_Width = 32;
output A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
reg A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
input [D_Width-1:0] A;
input [D_Width-1:0] B;

always@(A or B)
begin
if(A>B) A_gt_B = 1;
else if (A<B) A_lt_B = 1;
else if (A==0) A_eq_zero = 1;
else if (B==0) B_eq_zero = 1;
end

endmodule
 
prasunp@gmail.com wrote:

Hello:

I am trying to write some code for a comparator. Is it possible to
write the code as so

module comparator(A_lt_B, A_gt_B, A_eq_zero, B_eq_zero, A, B);

parameter D_Width = 32;
output A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
reg A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
input [D_Width-1:0] A;
input [D_Width-1:0] B;

always@(A or B)
begin
if(A>B) A_gt_B = 1;
else if (A<B) A_lt_B = 1;
else if (A==0) A_eq_zero = 1;
else if (B==0) B_eq_zero = 1;
end

endmodule
Click to expand...
1) you don't have statements for results of false.
2) you can have A<B and A==0 but your code will only provide A_lt_B.

Rather than if/elseif/elseif/elseif which will produce latches (if A==B
and A!=0) consider assigning the result variables directly as opposed to
the conditional statements, e.g. A_gt_B = (A>B);
 
This looks like the time for wire assignments :

wire A_lt_B = ( A &lt; B ) ? 1'b1 : 1'b0 ;
wire A_gt_B = ( A &gt; B ) ? 1'b1 : 1'b0 ;
wire A_eq_zero = ( A == {D_Width{1'b0}} ) ? 1'b1 : 1'b0 ;
wire B_eq_zero = ( B == {D_Width{1'b0}} ) ? 1'b1 : 1'b0 ;

- Your previous logic assumes that somehow these values are 0, unless
you set them to 1.
- only seems to allow for a value to set one condition, but you want it
parallel. so if A &gt; B, and B == 0, the B_eq_zero would not ever get
set.

-Art
 
Can I have these wire assignments in the always block.

Thanks you for suggestions
 
I guess it would be of no great use to write in in a always block. I
was just wondering If it was possible.
Thanks for all the help everyone
 
Can Compartors do comparision with signed numbers too?. Is it possible
to incorporate that in the code. Suppose the A was two's complement,
do I check the A[n-1] th bit for sign?

Thanks
 
General rule :

wire foo ;
assign foo = a &amp; b ;

is the same as :

reg foo ;
always @(a or b)
foo = a &amp; b ;

is the same as ( Verilog-2001 ) :

reg foo ;
always @(*)
foo = a &amp; b ;

As a general rule, if something can be expressed in 1 line, I make a
wire assigment out of it. If it gets too crowded, or needs multiple
lines, I use a "reg" and an "always @" block so the flow of logic is
clear.

Another rule, I try to follow, is don't write more than one variable in
an always block. sometimes doing 2 is fine, but more leads to the
problem of forgetting to assign the value in one possible set of
conditions thus infering a latch.

The opposite is even more true, "only ever assign a variable in 1
always block". Simulation race conditions can be avoided, this is
sometimes impossible to do with testbench signals like clock for
instance.

-Art
 
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