parameter pass

R

raghu

Guest
I have a problem in the following verilog code....

for(sel=0;sel<16;sel=sel+1)
begin
key= box(key,sel);
data= sub(arg1,agr2)
end

function [1:3] box;
input [1:3]key;
input sel;
begin
case(sel)
0: statements; // ex: key = statements;
1:statements;
2:statements;
and so on till 15:statements;
endcase

case(sel)
0: box= statements; // ex: box = key;
1: box=statements;
2: box=staements;
ans so on till 15: box=statements;
endcase
end
endfunction

Now the problem is "sel " parameter in box function is being passed
only for 2 rounds i.e sel=0 and sel=1. when sel increments to 2 the box
function takes again sel=0 and when sel increments to 3 box function
takes sel=1 ,when sel increments to 4 box takes again sel=0 and so on
......

Can anyone please tell me where the problem could be? why the box
function takes only sel parameter values as 0 and 1.

Hoping for the positive response.

Thanks & Regards,
Raghu
 
You should define your "sel" as "input [3:0] sel" in function box.
Otherwise it takes only LSB bit.

raghu wrote:
I have a problem in the following verilog code....

for(sel=0;sel<16;sel=sel+1)
begin
key= box(key,sel);
data= sub(arg1,agr2)
end

function [1:3] box;
input [1:3]key;
input sel;
begin
case(sel)
0: statements; // ex: key = statements;
1:statements;
2:statements;
and so on till 15:statements;
endcase

case(sel)
0: box= statements; // ex: box = key;
1: box=statements;
2: box=staements;
ans so on till 15: box=statements;
endcase
end
endfunction

Now the problem is "sel " parameter in box function is being passed
only for 2 rounds i.e sel=0 and sel=1. when sel increments to 2 the box
function takes again sel=0 and when sel increments to 3 box function
takes sel=1 ,when sel increments to 4 box takes again sel=0 and so on
.....

Can anyone please tell me where the problem could be? why the box
function takes only sel parameter values as 0 and 1.

Hoping for the positive response.

Thanks & Regards,
Raghu
 
Thanks a lot Micheal...


Michael wrote:
sel" in function box.
Otherwise it takes only LSB bit.

raghu wrote:
I have a problem in the following verilog code....

for(sel=0;sel<16;sel=sel+1)
begin
key= box(key,sel);
data= sub(arg1,agr2)
end

function [1:3] box;
input [1:3]key;
input sel;
begin
case(sel)
0: statements; // ex: key = statements;
1:statements;
2:statements;
and so on till 15:statements;
endcase

case(sel)
0: box= statements; // ex: box = key;
1: box=statements;
2: box=staements;
ans so on till 15: box=statements;
endcase
end
endfunction

Now the problem is "sel " parameter in box function is being passed
only for 2 rounds i.e sel=0 and sel=1. when sel increments to 2 the box
function takes again sel=0 and when sel increments to 3 box function
takes sel=1 ,when sel increments to 4 box takes again sel=0 and so on
.....

Can anyone please tell me where the problem could be? why the box
function takes only sel parameter values as 0 and 1.

Hoping for the positive response.

Thanks & Regards,
Raghu
 

Welcome to EDABoard.com

Sponsor

Back
Top