parameter in top module in XILINX ISE 6.1.02

[luigi raffo]

XILINX - ISE 6.1.02 - Modelsim 5.7 SE
In verilog I described my top module as follows:

module BoothMult (ck, load, ...)
parameter N=4;


I used testbench waveform to generate the testbench and I obtained:

module tbbooth;
....
defparam UUT.N = 4;
BoothMult UUT (
..ck(ck),
....


obviously it is ok pre-synthesis but not post (N parameter doesn't exist anymore).
It seems to me this is a software bug, please let me know if I'm wrong.
luigi