M
Mike
Guest
Hi,
In the 1364-1995 spec, it specifically states that if the RHS of a
defparam statement contains references to parameters, then those
parameters must be declared in the same module as the defparam
statement. I didn't see any such restriction for parameter
declarations, yet my verilog-xl simulator seems to not allow any
(implicit or expilcit) hierarchical references in parameter
declarations.
I am guessing that this is to simplfy parameter value resolution during
elaboration?
Thanks in advance,
Mike
----------------------------------------------
module top;
parameter p = 1'b1;
a a();
parameter q = a.p0;
endmodule
module a;
parameter p0 = 1'b1;
parameter p1 = p0;
parameter p2 = q;
parameter p3 = top.p0;
parameter p4 = top.a.p0;
endmodule
/*
Compiling source file "hparam.v"
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 5:
Error! Identifier (q) not declared
[Verilog-IDSND]
"hparam.v", 11:
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 12:
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 13:
4 errors
End of Tool: VERILOG-XL 05.30.002-s Jul 8, 2006 21:54:49
*/
In the 1364-1995 spec, it specifically states that if the RHS of a
defparam statement contains references to parameters, then those
parameters must be declared in the same module as the defparam
statement. I didn't see any such restriction for parameter
declarations, yet my verilog-xl simulator seems to not allow any
(implicit or expilcit) hierarchical references in parameter
declarations.
I am guessing that this is to simplfy parameter value resolution during
elaboration?
Thanks in advance,
Mike
----------------------------------------------
module top;
parameter p = 1'b1;
a a();
parameter q = a.p0;
endmodule
module a;
parameter p0 = 1'b1;
parameter p1 = p0;
parameter p2 = q;
parameter p3 = top.p0;
parameter p4 = top.a.p0;
endmodule
/*
Compiling source file "hparam.v"
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 5:
Error! Identifier (q) not declared
[Verilog-IDSND]
"hparam.v", 11:
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 12:
Error! Illegal reference in constant expression
[Verilog-IRCE]
"hparam.v", 13:
4 errors
End of Tool: VERILOG-XL 05.30.002-s Jul 8, 2006 21:54:49
*/