Paralleling FETS

H

Hammy

Guest
I'm thinking of using a dual mosfet in a SC-88 package (NTJD4401N), in
a current source.

The FET's will be controlled by an LMV611 opamp. They don't state in
the datasheet how well matched the pair is (threshold voltage and
Rdson).

I read a note from TI on paralleling FETS and it said that process
variations for Vt and Rdson for single FETS same production batch were
nowhere near the worst case datasheet specs.

Is it a good idea to use Dual FETS like that?

http://www.onsemi.com/pub_link/Collateral/NTJD4401N-D.PDF
 
"Hammy" <spamme@hotmail.com> wrote in message
news:rhibf41tb18jahhrdpgvidnbikjp8tmc86@4ax.com...
I'm thinking of using a dual mosfet in a SC-88 package (NTJD4401N), in
a current source.

The FET's will be controlled by an LMV611 opamp. They don't state in
the datasheet how well matched the pair is (threshold voltage and
Rdson).

I read a note from TI on paralleling FETS and it said that process
variations for Vt and Rdson for single FETS same production batch were
nowhere near the worst case datasheet specs.

Is it a good idea to use Dual FETS like that?

http://www.onsemi.com/pub_link/Collateral/NTJD4401N-D.PDF
Click to expand...
Google is very easy to use:


http://www.sampson-jeff.com/tcrobowar/motor1/para.htm

http://www.irf.com/technical-info/appnotes/an-941.pdf

http://www.microsemi.com/micnotes/APT0402.pdf

http://www.powerdesigners.com/InfoWeb/design_center/articles/MOSFETs/mosfets.shtm

http://www.fairchildsemi.com/an/AN/AN-558.pdf
 
On Wed, 15 Oct 2008 06:13:57 -0500, "Jon Slaughter"
<Jon_Slaughter@Hotmail.com> wrote:


Google is very easy to use:


http://www.sampson-jeff.com/tcrobowar/motor1/para.htm

http://www.irf.com/technical-info/appnotes/an-941.pdf

http://www.microsemi.com/micnotes/APT0402.pdf

http://www.powerdesigners.com/InfoWeb/design_center/articles/MOSFETs/mosfets.shtm

http://www.fairchildsemi.com/an/AN/AN-558.pdf



Yes I know I've already read all that and similar stuff in textbooks.
Click to expand...

If you want to get anal about it every question posed here as well as
SED could be answered by reading a book are googleing.

I post here to ask for practical advice i.e someone who actually has
experience doing circuit design and could maybe share insight. A
category which excludes you.
 
On Wed, 15 Oct 2008 06:51:43 -0400, Hammy <spamme@hotmail.com> wrote:

I'm thinking of using a dual mosfet in a SC-88 package (NTJD4401N), in
a current source.

The FET's will be controlled by an LMV611 opamp. They don't state in
the datasheet how well matched the pair is (threshold voltage and
Rdson).

I read a note from TI on paralleling FETS and it said that process
variations for Vt and Rdson for single FETS same production batch were
nowhere near the worst case datasheet specs.

Is it a good idea to use Dual FETS like that?

http://www.onsemi.com/pub_link/Collateral/NTJD4401N-D.PDF
Click to expand...
We've found big mismatches, like a volt of Vg, in discrete fets, all
from the same batch. Best to close a loop around each fet, or use big
source resistors.

John
 
"Hammy" <spamme@hotmail.com> wrote in message
news:3vmbf4hj9sqv49u0eop8uhf1ma9c9mi21r@4ax.com...
On Wed, 15 Oct 2008 06:13:57 -0500, "Jon Slaughter"
Jon_Slaughter@Hotmail.com> wrote:


Google is very easy to use:


http://www.sampson-jeff.com/tcrobowar/motor1/para.htm

http://www.irf.com/technical-info/appnotes/an-941.pdf

http://www.microsemi.com/micnotes/APT0402.pdf

http://www.powerdesigners.com/InfoWeb/design_center/articles/MOSFETs/mosfets.shtm

http://www.fairchildsemi.com/an/AN/AN-558.pdf



Yes I know I've already read all that and similar stuff in textbooks.

If you want to get anal about it every question posed here as well as
SED could be answered by reading a book are googleing.

I post here to ask for practical advice i.e someone who actually has
experience doing circuit design and could maybe share insight. A
category which excludes you.
Click to expand...
There was a lengthy thread about parallel MOSFETs last December. I did an
LTspice simulation, which showed good current sharing among several
devices, and when Phil freaked out about it, I did an actual breadboard
experiment that proved it works for real devices:

http://groups.google.com/group/sci.electronics.design/msg/c64478c824397da8

Essentially, the results were as follows:

==========================================================================

So I did an experiment. I connected four MOSFETs, HUF75645P, 100V, 75A,
310W, 0.014 ohm. Sources to GND. Gates tied together, through 100 ohms to a
pot across 10 VDC supply. Each drain to a 100 ohm resistor and a red LED to
+10 VDC.

Vgs: 2.50 2.60 2.73 2.86 3.00 3.20 3.50


Vd(1) 8.80 8.75 8.60 8.48 7.95 3.43 0.016
Vd(2) 8.80 8.76 8.62 8.51 8.15 4.56 0.018
Vd(3) 8.76 8.72 8.58 8.45 7.93 2.95 0.015
Vd(4) 8.79 8.76 8.63 8.53 8.21 5.40 0.020


LEDs were all about equal brightness and were barely lit at 2.73V and
fairly bright at 3.00V to 3.20V.


============================================================================

When called to task about the low current used for this test, I redid the
experiment:

http://groups.google.com/group/sci.electronics.design/msg/da059ef9c84d05fa?dmode=source

============================================================================

OK. I changed the circuit to source follower. Devices 1, 2, and 3 are
connected through 12 ohm 10 watt resistors to GND, device 4 has a 100 ohm
to GND. All drains connected to a 10 VDC supply. Gates in parallel through
100 ohms to a pot across the supply. Results:


Vg: 5.00 6.00 7.00 7.50 8.00 9.00 10.0 7.50(cold)


Vs(1) 2.25 3.13 4.11 4.65 5.13 6.12 7.11 4.53
Vs(2) 2.31 3.23 4.09 4.73 5.20 6.16 7.18 4.60
Vs(3) 2.18 3.12 4.09 4.60 5.09 6.07 7.06 4.27
Vs(4) 2.26 3.20 4.17 4.67 5.03 6.16 7.16 4.66


Paul
 
On Wed, 15 Oct 2008 08:45:17 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:


We've found big mismatches, like a volt of Vg, in discrete fets, all
from the same batch. Best to close a loop around each fet, or use big
source resistors.

John
Click to expand...
Thanks for the help John and Paul

Turns out the problem isnt the LMV611 ability to drive the FET a
FDN357N . The refrence was the problem TLVH431. I'm getting 2uS fall
times when I switch the refrence in and out.

This is the schematic: Pulsed current source.

http://i36.tinypic.com/vardi.png

Spice is more optimistic it shows sub 100nS rise fall times. These
measurments (see below) are taken at R3 positive input of the
LMV611.The rise time in the real world is 300 nS with fall time
greater then 2uS.

The mosfet is turning on and off 34nS rise/fall gate pulses. Theres
only 2pf at the input to the lmv611 so this isnt the problem. I did
test just the refrence portion with a switch by itself and got the
same results.

This is a spice sim result of the circuit showing

RED TRACE - Drain of NTS4001 (Cathode of TLVH431)
GREEN TRACE - R3 (Positive input of the LMV611)

http://i37.tinypic.com/a583o1.png

I tried placing the switch in different locations but it didnt solve
the problem.
 
On Thu, 16 Oct 2008 19:49:02 -0400, Hammy <spamme@hotmail.com> wrote:

On Wed, 15 Oct 2008 08:45:17 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:


We've found big mismatches, like a volt of Vg, in discrete fets, all
from the same batch. Best to close a loop around each fet, or use big
source resistors.

John

Thanks for the help John and Paul

Turns out the problem isnt the LMV611 ability to drive the FET a
FDN357N . The refrence was the problem TLVH431. I'm getting 2uS fall
times when I switch the refrence in and out.

This is the schematic: Pulsed current source.

http://i36.tinypic.com/vardi.png

Spice is more optimistic it shows sub 100nS rise fall times. These
measurments (see below) are taken at R3 positive input of the
LMV611.The rise time in the real world is 300 nS with fall time
greater then 2uS.

The mosfet is turning on and off 34nS rise/fall gate pulses. Theres
only 2pf at the input to the lmv611 so this isnt the problem. I did
test just the refrence portion with a switch by itself and got the
same results.

This is a spice sim result of the circuit showing

RED TRACE - Drain of NTS4001 (Cathode of TLVH431)
GREEN TRACE - R3 (Positive input of the LMV611)

http://i37.tinypic.com/a583o1.png

I tried placing the switch in different locations but it didnt solve
the problem.
Click to expand...
I think it may be the NTS4001 . I just tried the only logic level
through hole FET I have RFP30N06LE Rise times were 200nS and fall
times were 500nS. It Takes the driver 120 to 200nS to turn it
on/off.It has large Qg.

I'll solder in a new NTS4001 tommorrow and see if that fixes the
problem.
 
On Thu, 16 Oct 2008 19:49:02 -0400, Hammy <spamme@hotmail.com> wrote:

On Wed, 15 Oct 2008 08:45:17 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:


We've found big mismatches, like a volt of Vg, in discrete fets, all
from the same batch. Best to close a loop around each fet, or use big
source resistors.

John

Thanks for the help John and Paul

Turns out the problem isnt the LMV611 ability to drive the FET a
FDN357N . The refrence was the problem TLVH431. I'm getting 2uS fall
times when I switch the refrence in and out.

This is the schematic: Pulsed current source.

http://i36.tinypic.com/vardi.png

Spice is more optimistic it shows sub 100nS rise fall times. These
measurments (see below) are taken at R3 positive input of the
LMV611.The rise time in the real world is 300 nS with fall time
greater then 2uS.

The mosfet is turning on and off 34nS rise/fall gate pulses. Theres
only 2pf at the input to the lmv611 so this isnt the problem. I did
test just the refrence portion with a switch by itself and got the
same results.

This is a spice sim result of the circuit showing

RED TRACE - Drain of NTS4001 (Cathode of TLVH431)
GREEN TRACE - R3 (Positive input of the LMV611)

http://i37.tinypic.com/a583o1.png

I tried placing the switch in different locations but it didnt solve
the problem.
Click to expand...

In real life, the opamp may wind up when switch U13 is off, and it may
take a long time to recover. U13's capacitances may slow things, too.

But what is that 4-terminal box on the right? What is V4 about?

John
 
On Thu, 16 Oct 2008 20:06:13 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:


In real life, the opamp may wind up when switch U13 is off, and it may
take a long time to recover. U13's capacitances may slow things, too.

But what is that 4-terminal box on the right? What is V4 about?

John



The 4 terminal box is a FDN357N Mosfet model. Fairchild models have an
Click to expand...
extra terminal for setting the junction temp. The V4 source puts the
junction temp at 125 deg C. When I first starting getting models from
Fairchild with the extra terminal I didnt know what it was, someone
here posted how to use it. I havent gotten around to makeing a proper
symbol for the FET with the extra terminal.
 
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