Parallel to Serial and Serial to Parallel converters PISO SI

i need to design an eight bit version of each of these components. any
help?

thnaks in advance

 

[Mike Treseler]

andrew.abelovski@gmail.com wrote:

Parallel to Serial and Serial to Parallel converters
i need to design an eight bit version of each of these components.

Two of the simplest and most useful
hardware structures are counters
and shift registers.

Good luck.

-- Mike Treseler

 

[krby_xtrm]

if load = '1' then
tmp := data_in; -- load data first, tmp is a variable of size data_in
elseif clk'EVENT and clk='1' then
sdata <= tmp(cnt); -- cnt is a variable
cnt:= cnt +1; -- increment
end if;

 

[Dominik Domanski]

i need to design an eight bit version of each of these components. any
help?

thnaks in advance

Hi,
Parallel to Serial:
You can make it by setting a register (some signal std_logic_vector(7 downto
0) connected to parallel data port),and then just shift it
(serial_data<=parallel_register(7);parallel_register(7 downto
1)<=parallel_register(6 downto 0)).You shift as long as in other process
(with counter) you get 8 (for 8-bit parallel data).
Serial to Parallel:
You make it in opposite way
parallel_register(0)<=serial_data;parallel_register(7 downto
1)<=parallel_register(6downto 0) with counter to make it 8 times.

Dominik
d_domanski@tlen.pl