Parallel simulation consistency?

[Gary Thorpe]

Hi,

I am using ncvhdl, ncelab, and ncsim to perform some VHDL simulations. I
would like to know if doing the following would cause problems with the
simulations:

my_configuration
ncsim my_configuration &
ncelab -generic [another set of parameters] my_configuration
ncsim my_configuration &

I.e. can I elaborate the design, start simulating that, re-elaborate it with
different parameters, and start another simulation in parallel? Will this
cause any problems or inconsistencies?