Parallel Image Processing in VHDL

[mike]

I´m doing a Final Year project that consists in Parallel Image
Procesing. More specifically I must do a VHDL program to upload it
into an Spartan FPGA, with a serial input and a serial output. The
image has only black and white pixels (0-1), and I must create a
'processor' for each pixel and compare his color(0-1) with the pixels
around him(neighbourhood). With the result I must label the image and
detect edges.
I don´t have any experience in VHDL, and the project is assigned with
no possibility to change it. I´m using a shift register for the serial
input, and I was thinking of using arrays and the Heaviside local
operator, but always thinking that the program must be executed in
PARALEL!.
I´ve read a lot about algorithms, but I haven´t found any program that
suits my project or even aproximates it.
If I don´t finish the project, I will loss my work because I need the
bachelor degree to renew it.
I´m really frustrated and I don´t know what can I do. Please help

Thanks in advance, any suggestion that could help me will be
appreciated.

 

[Jerzy]

I´m doing a Final Year project that consists in Parallel Image
Procesing. More specifically I must do a VHDL program to upload it
into an Spartan FPGA, with a serial input and a serial output. The
image has only black and white pixels (0-1), and I must create a
[...]

Hi
Very interesting project.
Serial - what you mean row after row? How big is the image? What kind
of FPGA you can use?
You can load all image to fpga and process it parallel, whatever you
want to be done with it.
I would try detect edges by differential method - row after row, next
column after column, then summ this IMrow + IMcol + label.
It was first think I had after reading your mail. But of course I can
be wrong.

If you want use other formula for detect edges, write it, then we will
see.
I'm sure, everything could be solve.

Best regards

Jerzy Gbur

 

[mike_treseler]

gish_bcn wrote

I don´t have any experience in VHDL, and the project is >assigned with no
possibility to change it.

Then it is very unlikely that you will finish this
within a year. Consider changing majors to something
that truly interests you.
I am guessing that you have much completed work to lose.

-- Mike Treseler

 

[mike_treseler]

Make that:
"I am guessing that you *don't* have much completed work to lose."

 

[Ralf Hildebrandt]

mike wrote:

I´m doing a Final Year project that consists in Parallel Image
Procesing. More specifically I must do a VHDL program to ...

VHDL is not a programming language. It is hardware description language.

upload it
into an Spartan FPGA, with a serial input and a serial output. The
image has only black and white pixels (0-1), and I must create a
'processor' for each pixel and compare his color(0-1) with the pixels
around him(neighbourhood). With the result I must label the image and
detect edges.

What does "label" mean? Do you have to provide a output signal that says
"there are edges" (or whatever)?

I don´t have any experience in VHDL, and the project is assigned with
no possibility to change it. I´m using a shift register for the serial
input, and I was thinking of using arrays and the Heaviside local
operator, but always thinking that the program must be executed in
PARALEL!.

Ok, but again: VHDL is not a programming language and therefore there is
no "parallel program" to solve the problem.
You have to think about how to implement the algorithm in hardware.

First of all: What is your profession? Are you a software programmer or
do you have basic knowledge about digital circuits? Did you visit
lectures of electrical engineering (for some semesters)?


Two basic things exist in hardware: Combinational logic and sequential
cells.

Combinational logic is just a bunch of gates, that outputs something
dependent on the input.

a <= b XOR c;
d <= e+f;
g <= h*i;


Two sequential cells exist: Latches and Flipflops.

A Latch opens it's input, as long as an "enable-signal" is active.
Otherwise it stores the data independend from the input.

process(enable,data)
begin
if (enable='1') then
latch_out<=data;
end if;
end process;

A Flipflop stores it's input during the edge of the clock signal.

process(clk)
begin
if rising_edge(clk) then
ff_out<=data;
end if;
end process;

Sequential cells can be used to build registers, shift registers, state
machines and so on.


For basic stuff this is all you need. In many cases a VHDL design is
nothing more than the combination and connection of the mentioned
things. The problem is to find a realisation for an algorithm, that fits
to these basic things.

Ralf

 

[mike]

First of all, thanks to everybody that is helping me.
Second, please excuse my poor english.
And now, I´m going to explain a bit more the project with an example.
Let´s supose that I´ve this image (no matter if it´s small, it´s only
to show the problem):

(1,1,0,0)
(1,1,0,0)
(0,0,1,1)
(0,0,1,1)

The image will enter to the FPGA through a PIN input, and will be
stored in a shift register.
Once the image is in the FPGA, I was thinking to apply Heaviside to
every "1" pixel of the imgage f.e: Hi,j=h(h(bi,j +bi,j-1 +bi-1,j-1
-1)+h(bi,j +bi-1,j-1 -1), when bi,j is the binary bit value of each
pixel.

After each parallel-shrink operation, the image will change like this:

1ş(0,1,0,0)
(1,1,0,0)
(0,0,1,1)
(0,0,1,1)

2ş(0,0,0,0)
(0,1,0,0)
(0,0,1,1)
(0,0,1,1)

3ş(0,0,0,0)
(0,0,0,0)
(0,0,1,1)
(0,0,1,1)

4ş(0,0,0,0)
(0,0,0,0)
(0,0,0,1)
(0,0,1,1)

5ş(0,0,0,0)
(0,0,0,0)
(0,0,0,0)
(0,0,0,1)

6ş(0,0,0,0)
(0,0,0,0)
(0,0,0,0)
(0,0,0,0)

What I need is that the final image looks like this:

(0,0,0,0)
(0,1,0,0)
(0,0,0,0)
(0,0,0,1)

To get that, I made a condition:

(i-1,j)=0 & (i,j-1)=0 & [(i+1,j)=1 | (i,j+1)=1]

that condition will avoid the "killig" of isolated "1"´s.

In the image above, we can see two objects, and from here I can label
the image, count the objects, etc...

What do you think about the algorithm?. My problem is how to translate
it into VHDL (I know for sure that I will need to work with arrays,
but I don´t know how). I´m an electronic engineer and I´ve a bit
experience on C++, Pascal, Java but programmming it´s not my best.

Than you for reding me, and again, any suggestion will be appreciated.

 

[E.S.]

mike wrote:

First of all, thanks to everybody that is helping me.
Second, please excuse my poor english.
And now, I´m going to explain a bit more the project with an example.
Let´s supose that I´ve this image (no matter if it´s small, it´s only
to show the problem):

...

What do you think about the algorithm?. My problem is how to translate
it into VHDL (I know for sure that I will need to work with arrays,
but I don´t know how). I´m an electronic engineer and I´ve a bit
experience on C++, Pascal, Java but programmming it´s not my best.

Than you for reding me, and again, any suggestion will be appreciated.

I'm probably off here, but if you look (google?) for somebody who
implemented Conways game of life in VHDL, you probably close already to
what you're trying to implement ...

cheers,
emanuel

P.S. Try to put "conway game of life vhdl" into google ;-)

 

[Hal Murray]

What do you think about the algorithm?. My problem is how to translate
it into VHDL (I know for sure that I will need to work with arrays,
but I don´t know how). I´m an electronic engineer and I´ve a bit
experience on C++, Pascal, Java but programmming it´s not my best.

I suggest that you debug the algorithims using normal software.

VHDL is not a programming language. It's a hardware description
language. After you get the algorithims debugged, you have to
turn them into hardware. (Keep that it mind when selecting your
ideas.) After you figure out what the hardware should look like,
then you can write the VHDL to make that hardware.

It may be that your problem should be run on a CPU rather
than special hardware.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Weng Tianxiang]

Mike,
1. I am sure that your idea is right: it can be done in parallel with
serial data input stream of a frame with a FPGA; And I think the method
is best suitable for your project, not with a CPU;
2. I agree with your idea: VHDL is another programming language;
3. I agree with another Mike's idea: you cannot finish it within one
year;
4. I think you have to sharp your FPGA technology before taking the
job. If you insists to take the project, you may ask for extension of 1
year of study. Currently you are a college student and taking the
project is risky: you certainly will not finish the job within one
year.

Weng