Parallel execution of Systemc code

// Testbench
rst=true; wait(10, SC_MS);
rst=false; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.

 

[HT-Lab]

On 06/01/2015 09:15, muyihwah@gmail.com wrote:

// Testbench
rst=true; wait(10, SC_MS);
rst=false; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

I suspect you pasted the wrong code snippet? The code above is sequential.

Hans
www.ht-lab.com

 

Am Dienstag, 6. Januar 2015 13:30:59 UTC+1 schrieb HT-Lab:

On 06/01/2015 09:15, muyihwah@gmail.com wrote:
// Testbench
rst=true; wait(10, SC_MS);
rst=false; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

I suspect you pasted the wrong code snippet? The code above is sequential.

Hans
www.ht-lab.com

Please could you explain what shows the code to be sequential.

 

[glen herrmannsfeldt]

muyihwah@gmail.com wrote:

(snip, someone wrote)

I am used to VHDL which runs in parallel, but I finding it
difficult to understand/if Systemc code run in parallel like
the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

(snip)

> Please could you explain what shows the code to be sequential.

Personally, I am against the idea of things like SystemsC.

Well, I use structural verilog mostly, with behavioral verilog only
for things that can't be done otherwise, like registers.

But if one is used to wiring up gates and flip-flops, it isn't
hard to think about writing that down, and, as with TTL logic,
everything happening in parallel.

SystemsC pretends to look like serial C, and makes you believe that
you can design logic with serial thinking. Even more, it might make
you believe that you can port serial programs to parallel logic
without change.

My favorite use for FPGAs is systolic array implementations of
dynamic programming algorithms. They look very different from the
serial (C) implementations. There is no useful porting of C code.

-- glen

 

[Alan Fitch]

On 06/01/15 19:13, muyihwah@gmail.com wrote:

Am Dienstag, 6. Januar 2015 13:30:59 UTC+1 schrieb HT-Lab:
On 06/01/2015 09:15, muyihwah@gmail.com wrote:
// Testbench
rst=true; wait(10, SC_MS);
rst=false; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

I suspect you pasted the wrong code snippet? The code above is sequential.

Hans
www.ht-lab.com

Please could you explain what shows the code to be sequential.

They are obviously not declarations, therefore they are statements in a
single C++ function, and hence are sequential.

regards
Alan

--
Alan Fitch

 

On Wednesday, January 7, 2015 12:48:41 AM UTC+1, Alan Fitch wrote:

On 06/01/15 19:13, muyihwah@gmail.com wrote:
Am Dienstag, 6. Januar 2015 13:30:59 UTC+1 schrieb HT-Lab:
On 06/01/2015 09:15, muyihwah@gmail.com wrote:
// Testbench
rst=true; wait(10, SC_MS);
rst=false; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

I suspect you pasted the wrong code snippet? The code above is sequential.

Hans
www.ht-lab.com

Please could you explain what shows the code to be sequential.


They are obviously not declarations, therefore they are statements in a
single C++ function, and hence are sequential.

regards
Alan

--
Alan Fitch

Thanks a lot for the response. Could you please point me to some online resources or books that might provide detailed explanations.

 

[HT-Lab]

On 06/01/2015 23:43, glen herrmannsfeldt wrote:

Hi Glen,

muyihwah@gmail.com wrote:

(snip, someone wrote)

I am used to VHDL which runs in parallel, but I finding it
difficult to understand/if Systemc code run in parallel like
the example above.

SystemC's simulation model is very similar to VHDL (incl. delta cycles
etc).

(snip)

Please could you explain what shows the code to be sequential.

Personally, I am against the idea of things like SystemsC.

Why? It is just another RTL language (library).

Well, I use structural verilog mostly, with behavioral verilog only
for things that can't be done otherwise, like registers.

Behavioural Verilog to model a Register?

But if one is used to wiring up gates and flip-flops, it isn't
hard to think about writing that down, and, as with TTL logic,
everything happening in parallel.

SystemsC pretends to look like serial C,

SystemC doesn't look at all like serial C, SystemC is processes,
signals, ports, hierarchy, i.e all the constructs you will find in
Verilog/VHDL. If you want to do architectural exploration you need to
use a block of C/C++ code and not SystemC. SystemC adds concurrency to
C/C++.

and makes you believe that
you can design logic with serial thinking. Even more, it might make
you believe that you can port serial programs to parallel logic
without change.

I give you the "without a change" but other than that you should have a
look at the latest ESL tools capability like Catapult8 and Cynthesizer5,
you will be impressed.

My favorite use for FPGAs is systolic array implementations of
dynamic programming algorithms. They look very different from the
serial (C) implementations. There is no useful porting of C code.

I am sure you can model a systolic array in plain old C, in SystemC it
should be as easy as Verilog or VHDL,

Regards,
Hans.
www.ht-lab.com

-- glen

 

// Testbench
rst=true; wait(10, SC_MS);
rstĂşlse; in1=8; in2=2; in3=3; in4=6; sel=2;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl; rst=true; sel = 0;
wait(50, SC_MS);
cout << "selected data:" << out << " " << endl;


I am used to VHDL which runs in parallel, but I finding it difficult to
understand/if Systemc code run in parallel like the example above.

---------------------
Can I suggest some simple examples of systemc:
My First systemC program
systemC debug with SC_TIME Tip
Simple multiplier and a test-bench in systemC
ETHERNET packet scv RANDOMIZATION in systemC
http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html

---------------------------------------
Posted through http://www.FPGARelated.com