par problems with modular design for partial reconfiguration

[Nachiket Kapre]

Hi,
I am currently having a design with multiple reconfigurable modules
implemented as separate edifs. I've followed to modular design
instructions from the xilinx documentation and have managed to get
ngdbuild and map to work fine on all my modules. When I try to do a
PAR, after the placement is done, the router takes 15 minutes to start
dumping results onto the console. But, once it starts routing, the
process seems to finish off in a couple of seconds. The design it is
trying to route is a collection of 8 2:1 multiplexers. I dont see why
it should take 15 minues for such a small design. The area constraints
for the design also seem to be correct. Any ideas why the long
runtimes?

device = xc2v6000

p.s. does it matter for routing if i organise my modules in columns or
rows, assuming they span the entire column/row? does it affect the
time it takes to route an area which spans the breadth of the device
rather than the height?

regards,
nachiket.

 

[Kelvin @ SG]

is it becuase the area is way too big for your codes?

i had one pexerience when my reconfiguration module is 58 slices, and the
area allocated to it is 3072 slices.
it took over two hours to route that small module...fixed module is 3000+
slices in an area of 30000 slices, and it
took 10 minutes only...In the trial synthesis, I will use an xc2v2000 to
replace my xc2v6000 and see how it works...

I also found that, Route Phase 1 takes most of the time, while other 8
stages takes only a fraction of the total time...

In the tutorials I created at home, the slice numbers are 759(fixed) out of
1536, 292/338(reconfigurable) out of 1,536,
the whole flow, from synthesis to assembly, only took 20 minutes...

Hope you could share your experiences after you finished the project...

Best Regards,
Kelvin...






Nachiket Kapre <nachikap@yahoo.com> wrote in message
news:eadce17c.0401182056.482e630f@posting.google.com...

Hi,
I am currently having a design with multiple reconfigurable modules
implemented as separate edifs. I've followed to modular design
instructions from the xilinx documentation and have managed to get
ngdbuild and map to work fine on all my modules. When I try to do a
PAR, after the placement is done, the router takes 15 minutes to start
dumping results onto the console. But, once it starts routing, the
process seems to finish off in a couple of seconds. The design it is
trying to route is a collection of 8 2:1 multiplexers. I dont see why
it should take 15 minues for such a small design. The area constraints
for the design also seem to be correct. Any ideas why the long
runtimes?

device = xc2v6000

p.s. does it matter for routing if i organise my modules in columns or
rows, assuming they span the entire column/row? does it affect the
time it takes to route an area which spans the breadth of the device
rather than the height?

regards,
nachiket.

 

[Steve Casselman]

p.s. does it matter for routing if i organise my modules in columns or
rows, assuming they span the entire column/row? does it affect the
time it takes to route an area which spans the breadth of the device
rather than the height?

It is better to line up your muxes vertically. That is how the configuration
memory is set up. If you put your muxes all across the top, for example, You
will have to reload the whole device. If you line them up along a set of
columns then you only have to reconfigure the columns (not counting any
routes that go across horizontally).

Steve

 

[Ray Andraka]

Try constraining them to particular places. Depending on your
constraints, it may be taking the placer some time to come up with a
satisfactory placement, or may be taking the router a long time to route
the mess the placer made. Also, you'll want to organize them as a column
to minimize the reconfiguration time (reconfig happens by column), as well
as to match up to any arithmetic you might have in the design.

Nachiket Kapre wrote:

Hi,
I am currently having a design with multiple reconfigurable modules
implemented as separate edifs. I've followed to modular design
instructions from the xilinx documentation and have managed to get
ngdbuild and map to work fine on all my modules. When I try to do a
PAR, after the placement is done, the router takes 15 minutes to start
dumping results onto the console. But, once it starts routing, the
process seems to finish off in a couple of seconds. The design it is
trying to route is a collection of 8 2:1 multiplexers. I dont see why
it should take 15 minues for such a small design. The area constraints
for the design also seem to be correct. Any ideas why the long
runtimes?

device = xc2v6000

p.s. does it matter for routing if i organise my modules in columns or
rows, assuming they span the entire column/row? does it affect the
time it takes to route an area which spans the breadth of the device
rather than the height?

regards,
nachiket.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Nachiket Kapre]

"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<400b1764@news.starhub.net.sg>...

is it becuase the area is way too big for your codes?

wel actually it is! the muxes hardly take up 5-10 SLICEs whereas i
give an area constraint that spans the entire column! I' trying to
pack in more l;ogic into this column and will see what happens from
there on.

I also found that, Route Phase 1 takes most of the time, while other 8
stages takes only a fraction of the total time...

Yeah that was my experience as well..wonder how the router works ?

In the tutorials I created at home, the slice numbers are 759(fixed) out of
1536, 292/338(reconfigurable) out of 1,536,
the whole flow, from synthesis to assembly, only took 20 minutes...

So some runs of the router on certain mux columns in my design takes
seconds while the rest of the runs take about half an hour.. i think i
should try running them as separate designs with the same area
constraints without modular design flow to see if it takes just as
much time to do the routing..

Hope you could share your experiences after you finished the project...

certainly...

nachiket.

 

[Nachiket Kapre]

Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...

Try constraining them to particular places.
I'm working on creating new constraint files to nail the muxes down to

specific slices within the column. hope it works..

Depending on your

constraints, it may be taking the placer some time to come up with a
satisfactory placement, or may be taking the router a long time to route
the mess the placer made.

So the placer seems to be finishing off its job in abt 10 seconds.
I still dont understand how badly can a placer mess up on a design
this simple!...8 2:1 muxes?

Also, you'll want to organize them as a column

to minimize the reconfiguration time (reconfig happens by column), as well
as to match up to any arithmetic you might have in the design.

point noted.

thanks,
nachiket.

 

[Ray Andraka]

take a look at what the placer did by opening the floorplanner. I'll guarantee it ain't
pretty.

Nachiket Kapre wrote:

Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...
Try constraining them to particular places.
I'm working on creating new constraint files to nail the muxes down to
specific slices within the column. hope it works..

Depending on your
constraints, it may be taking the placer some time to come up with a
satisfactory placement, or may be taking the router a long time to route
the mess the placer made.

So the placer seems to be finishing off its job in abt 10 seconds.
I still dont understand how badly can a placer mess up on a design
this simple!...8 2:1 muxes?

Also, you'll want to organize them as a column
to minimize the reconfiguration time (reconfig happens by column), as well
as to match up to any arithmetic you might have in the design.

point noted.

thanks,
nachiket.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Nachiket Kapre]

ok, i am trying to get the module placed manually but and am
encountering the following problems in map:-

1. if i try to place all the components in the module (i have a
structural code with xilinx library components) i get an error in map
saying "active module missing". so when to get arond that if i remove
even a single constraint from the ucf, the active module magically
reappears. the par still fails saying unroutable design with 38 nets.
2. if i try to assign constraints to internal nets that connect
modules together using the PIN constraint (is this really
necessay?....the modular design doc. refers to these signals as pseudo
logic in the ucf). i did seem to get better routing results with only
9 unrouted nets as against 38 unrouted in case.(1)

i still am completely at a loss to understand why a design with 16 2:1
muxes with 16 flops given an area constraint of half a column of width
4 SLICEs struggles with routing. also, when doing modular design, does
the router try to route the upper level signals?..because the router
quotes a large number of 134 unrouted nets to start off for the above
design. how does the modular design methodology deal with having to
route the top-level signal like clk,reset of fpga-io?..i sure hope it
doesn't bother itself with those signals while routing a module.

regards,
nachiket.

Ray Andraka <ray@andraka.com> wrote in message news:<400CB198.E254D27D@andraka.com>...

take a look at what the placer did by opening the floorplanner. I'll guarantee it ain't
pretty.

Nachiket Kapre wrote:

Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...
Try constraining them to particular places.
I'm working on creating new constraint files to nail the muxes down to
specific slices within the column. hope it works..

Depending on your
constraints, it may be taking the placer some time to come up with a
satisfactory placement, or may be taking the router a long time to route
the mess the placer made.

So the placer seems to be finishing off its job in abt 10 seconds.
I still dont understand how badly can a placer mess up on a design
this simple!...8 2:1 muxes?

Also, you'll want to organize them as a column
to minimize the reconfiguration time (reconfig happens by column), as well
as to match up to any arithmetic you might have in the design.

point noted.

thanks,
nachiket.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759