G
Gary Crean
Guest
Does anybody have any verilog code for a PAL Tv video sync output ?
J
Jonathan Bromley
Guest
On Thu, 28 Jul 2005 22:15:15 GMT, "Gary Crean" <a@a.com> wrote:
construct an appropriate composite signal? Or do you need all
the other stuff: burst gate, black-level clamp gate, active
video enable? What about manufacturing the colour-burst signal
(not easy, if you want rigorous PAL compliance)? How picky are
you about getting all the equalisation and other guff right
during frame flyback - do you need broadcast-quality 100%
compliant, or are you satisfied with anything that will
reliably sync-up an ordinary TV receiver?
The simplest version is only an hour or so of coding effort,
and I've probably got one tucked away somewhere. Doing it
properly is a serious enterprise, and I definitely haven't
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
How much of it do you want? Just the syncs, so that you can
construct an appropriate composite signal? Or do you need all
the other stuff: burst gate, black-level clamp gate, active
video enable? What about manufacturing the colour-burst signal
(not easy, if you want rigorous PAL compliance)? How picky are
you about getting all the equalisation and other guff right
during frame flyback - do you need broadcast-quality 100%
compliant, or are you satisfied with anything that will
reliably sync-up an ordinary TV receiver?
The simplest version is only an hour or so of coding effort,
and I've probably got one tucked away somewhere. Doing it
properly is a serious enterprise, and I definitely haven't
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
R
raul
Guest
Gary Crean wrote:
signal only with accurate timing or the complete PAL composite signal
from a 656-4 8-bit YCbCr input?
RAUL
Are you talking about code that would drive a DAC to generate a sync
signal only with accurate timing or the complete PAL composite signal
from a 656-4 8-bit YCbCr input?
RAUL
G
Gary Crean
Guest
"raul" <raulizahi@gmail.com> wrote in message
news:1122789832.691042.223340@g47g2000cwa.googlegroups.com...
I've got the HSync stuff ok. It's just the 1/2 line VSync pulses that are
doing my head in.
news:1122789832.691042.223340@g47g2000cwa.googlegroups.com...
Greyscale an image.
I've got the HSync stuff ok. It's just the 1/2 line VSync pulses that are
doing my head in.
J
Jonathan Bromley
Guest
On Mon, 01 Aug 2005 18:48:59 GMT, "Gary Crean"
<a@a.com> wrote:
Serrations) on EVERY line, but you don't bother to use them
on most of the lines. During frame synch, however, you stir
together the EQ and SERR pulses to create the required
serrated synch. This mixing of the synchs is controlled
by a line count value, but you'll also need to know the
half-line count (flipped from 0 to 1 every EQ, halfway
through the line).
It's a PITA, but not too hard once you sit down and slug
through it a half-line at a time.
Think in terms of a state machine that advances through a
sequence of states at half-line time.
Make sure your final synch output is registered, to avoid
embarrassing glitches. Make sure your active-pixel counter
value is duly pipelined to take account of the delay in
synch that's introduced by that and other registers.
Still looking for the NTSC/PAL synch generator I wrote
six years ago...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
<a@a.com> wrote:
The trick is to generate EQ and SERR pulses (Equalisation and
Serrations) on EVERY line, but you don't bother to use them
on most of the lines. During frame synch, however, you stir
together the EQ and SERR pulses to create the required
serrated synch. This mixing of the synchs is controlled
by a line count value, but you'll also need to know the
half-line count (flipped from 0 to 1 every EQ, halfway
through the line).
It's a PITA, but not too hard once you sit down and slug
through it a half-line at a time.
Think in terms of a state machine that advances through a
sequence of states at half-line time.
Make sure your final synch output is registered, to avoid
embarrassing glitches. Make sure your active-pixel counter
value is duly pipelined to take account of the delay in
synch that's introduced by that and other registers.
Still looking for the NTSC/PAL synch generator I wrote
six years ago...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.