PADS/ESD cells in TSMC & UMC 0.18u kits?

S

spectrallypure

Guest
Hello everybody! Sorry for this not-so-on-the-topic question...

My research group has just been granted access to the 0.18u mixed
signal Cadence design kits for both TSMC and UMC foundries, which we
plan to use in order to implement a full-custom design. But to our
surprise, there are no PAD or ESD protection cells at all in these
design kits!! I have installed and browsed the libraries provided in
these design kits and all haven't been able to find a single periphery
cell. Now I wonder if these kits provide any of these cells at all, or
if the designer has to design and layout all them manually!!! :S
Does anybody know where are these cells located/supplied?

I have noticed in the www that many people mention the use of ARM/
Artisan IO cells... is this the only resource for IO/ESD cells for the
aforementioned processes? Are there any non-commercial alternatives?

Thanks in advance for any help/ideas!

Regards,

Jorge.

P.S. By the way, other than the obvious, I also need the PAD/ESD cells
because I need to take into account the parasitic loading of these
structures in the early stages of our design.
 
Hi Jorge,

I have no experience with the UMC design platforms but the other
Foundry (at the mentioned technology node) does not provide any of
your target libraries as far as I know. So it is worth looking at the
two other companies you've mentioned above unless you're fit enough (I
mean you or your team/company) to design that IOs/Pads. Well It's not
that easy and needs to be qualified for the given process and
application which is not straight forward really.

Don't ask me my opinion about foundries that does not supply a full
EDA design package (PDK + Digital Corlibs + IOs + Memories ...) I
could be very rude ...

Well, It's may be worth asking those foundries in case they have got
something up sleeves ...

Good luck anyway !

Riad.
 
I have noticed in the www that many people mention the use of ARM/
Artisan IO cells... is this the only resource for IO/ESD cells for the
aforementioned processes? Are there any non-commercial alternatives?
Click to expand...
Both foundries are supported by many different IP providers. ARM, Faraday, Virage Logic to name a few.

ARM and Faraday both provide libraries free-of-charge, see
http://www.arm.com/products/physicalip/product_overview.html and
http://freelibrary.faraday-tech.com. Foundries also have in-house and sponsored libraries. You
should get in touch with them for these things.

Unless you're in a university, which seems to be the case, then they'd rather let you deal with your
intermediary (MOSIS, Europractice, CMP or whoever).


For non-commercial alternatives, there's a library available from Virginia Tech for TSMC 0.18 and
0.25 processes. See
http://www.vtvt.ece.vt.edu/vlsidesign/cell.php.

There's also Oklahoma state university at http://avatar.ecen.okstate.edu/projects/scells/download.php

Not sure on the quality of these cells free cells, though. And I'm not sure if they include I/O
cells, never used them myself.


Cheers,
Stéphane
 
Europractice grant access to Analog and Digital IO Pads from Faraday
IP provider. Faraday Tech has included Analog ESD cells to
Europractice portfolio recently. But be informed that this cells has
neither schematic views for simulation nor physical layout views. You
got only lef, def files with net layers and they replace IO cells with
physical ones when you send the chip for fabrication. I used these
cells but I can not simulate any cells for example I would like to
know the leakage values of Analog ESD cells.

Ozgur

On Jun 9, 5:11 pm, spectrallypure <jorgela...@gmail.com> wrote:
Hello everybody! Sorry for this not-so-on-the-topic question...

My research group has just been granted access to the 0.18u mixed
signal Cadence design kits for both TSMC and UMC foundries, which we
plan to use in order to implement a full-custom design. But to our
surprise, there are no PAD or ESD protection cells at all in these
design kits!! I have installed and browsed the libraries provided in
these design kits and all haven't been able to find a single periphery
cell. Now I wonder if these kits provide any of these cells at all, or
if the designer has to design and layout all them manually!!! :S
Does anybody know where are these cells located/supplied?

I have noticed in the www that many people mention the use of ARM/
Artisan IO cells... is this the only resource for IO/ESD cells for the
aforementioned processes? Are there any non-commercial alternatives?

Thanks in advance for any help/ideas!

Regards,

Jorge.

P.S. By the way, other than the obvious, I also need the PAD/ESD cells
because I need to take into account the parasitic loading of these
structures in the early stages of our design.
Click to expand...
 
Thanks so much for the information. I contacted Europractice (which is
our EDA & foundry provider) with regard to the Artisan cells for TMSC,
but unfortunately they don't support them. So I contacted ARM
directly, and they told me they don't directly provide those to
universities, and that I should refer to an intermediary distributor
like MOSIS, with whom we don't have any account/membership :(

So, before going through the painful amount of paperwork and time that
would mean affiliating to another foundry intermediary, I would
appreciate if someone can comment on the type of IO/ESD cells
available from Artisan for TSMC processes... do they allow for
parasitics annotation / simulation in Analog Environment? I checked
Faraday cells for UMC's processes, and as Ozgur said they don't
provide this functionality. I would really like to know if Artisan
cells are of the same type or if they have better simulation
capabilities.

In the meantime I'll give a look to those free academic cells...
thanks again for the help.

Regards,

Jorge.
 
spectrallypure wrote:
So, before going through the painful amount of paperwork and time that
would mean affiliating to another foundry intermediary, I would
appreciate if someone can comment on the type of IO/ESD cells
available from Artisan for TSMC processes... do they allow for
parasitics annotation / simulation in Analog Environment? I checked
Faraday cells for UMC's processes, and as Ozgur said they don't
provide this functionality. I would really like to know if Artisan
cells are of the same type or if they have better simulation
capabilities.
Click to expand...
http://www.mosis.com/Technical/Designsupport/artisan-university.html

As a general rule, you'll always get frontend packages from those distributors. These're are ok for
digital, but it can be a pain for mixed designs.

If you motivate your request, you should probably be able to get the full layouts after signing
proper NDAs if applicable. Try first with your intermediary ; others will automatically bounce you
back to them anyway.

Of course, this can take time...



Stéphane
 
Hello Stéphane! Thanks for the link. I read a bit around it, but at
http://www.mosis.com/Technical/Designsupport/artisan-instantiate.html,
they finally state:

"ADDITIONAL RESTRICTIONS:
-You are not permitted to see the resulting complete GDS. MOSIS will
not provide you with the GDS for your instantiated layout.
-MOSIS cannot make any meaningful DRC results available, as the DRC
polygons reveal details of the ARM cell layouts.
-You cannot obtain cell layouts from MOSIS, nor will MOSIS refer you
to ARM to obtain them."

I think this is kind of conclusive, so I believe it might be wiser to
point to other foundries providing full design kits. The problem is
that so far the only one we know that provides fully-accessible IO/ESD
cells is Austriamicrosystems, which unfortunately doesn't have any
0.18um or smaller processes :( It's a real pity, because their design
kits are the most comprehensive, well documented and instructive ones
I've seen so far; other foundries' kits assume you hold a PhD in solid
state process engineering, have taped out designs since 1980, and have
12-inch wafers for breakfast, by the way! ;)

...According to your experience, do you know of any (university-
accessible) foundries that work in very deep submicron, and provide
fully-accessible IO/ESD cells on their design kits?

Thanks again for any help.

Regards,

Jorge.
 
...According to your experience, do you know of any (university-
accessible) foundries that work in very deep submicron, and provide
fully-accessible IO/ESD cells on their design kits?
Click to expand...
Nope...

Well I still think that you can get them. Now you've seen that it's not easy though... The real
question I guess is do you *really* need them ?



Stéphane
 
question I guess is do you *really* need them ?
Click to expand...
Yes, unfortunately. I am working on new type of output buffer for
pulsed communications, and the prototype I did in AMS' 0.35um worked
fine until I added the analog IO pads... then the capacitive loading
of the pads corrupted (sucked away) the pulses significantly, and the
ESD clamps between VDD and VSS generated a stray capacitive path that
resonated with the package/pin parasitic inductances... a whole
mess! :O

Seems that I will have to stick to this kit anyway...
 
Jorge,

You can ask to access to the ST's design-kits from CMP.
(130nm, 90nm, 65nm, 45nm)
You just need to fill out the online form :
http://cmp.imag.fr/products/DK/?p=dkrequest

Kholdoun


spectrallypure wrote:
question I guess is do you *really* need them ?

Yes, unfortunately. I am working on new type of output buffer for
pulsed communications, and the prototype I did in AMS' 0.35um worked
fine until I added the analog IO pads... then the capacitive loading
of the pads corrupted (sucked away) the pulses significantly, and the
ESD clamps between VDD and VSS generated a stray capacitive path that
resonated with the package/pin parasitic inductances... a whole
mess! :O

Seems that I will have to stick to this kit anyway...
Click to expand...
 
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