packet switched Network on chip

hello
i need the NoC project coding of vhdl . yaa in this
abstract is
a simple switch has five bi-directional ports connnecting
four neighbor switches with a local IP(Intellectual Property) cores
reuse .They employ a XY Routing algorithm with input Queue buffers.
The project main objective is a devlop switch with a small area
enabling its immediate practical use and acheving superior bandwidth
to conventional Intra chip modules

 

[mayank.bangalore@gmail.co]

But I think most of the coding for NOC kind of application, we need to
look towards SystemC kind of languages rather than VHDL.

As my understandnig goes, VHDL will become too complex and become
unmanageable, to integrate IP cores on even two ports. and
Implementing a XY routing Algorithm in VHDL wont give you much leverage
as much you can dervie from SystemC.

Regards
Mayank

 

[Kim Enkovaara]

mayank.bangalore@gmail.com wrote:

But I think most of the coding for NOC kind of application, we need to
look towards SystemC kind of languages rather than VHDL.

SystemC is very immature if something needs to be synthesized as a real
hardware. For modeling and design exploration it can be a good
alternative.

As my understandnig goes, VHDL will become too complex and become
unmanageable, to integrate IP cores on even two ports. and
Implementing a XY routing Algorithm in VHDL wont give you much leverage
as much you can dervie from SystemC.

I'd say that for things like that SystyemC is not the best choise.
In VHDL/Verilog generate can be quite handy if you need to integrate
many identical cores etc. Most of the worlds chips are done with
VHDL/Verilog and they integrate huge amount of IP all the time

--Kim