Packet header implement in Verilog

[Verilog_Maan]

Hello All

I am designing packet header and I am stuck with very
simple problem and I an beginer of Verilog so I need your help.

packet is made up 80 bit and this 80 bit is devided into 20 bit phit
and this each phit is made up of various sub filed.I want to comapre
each sub filed with each 32 AND(bit wise AND) combination of 6
variable each is 32 bit long.how i will do?[Note:this filed varies
between 2 bits to 15 bits. In short i am doing mask and match].here is
my code and i am not getting the ouput so please help me with this.I
know i have to use byte comparator but how?
i also want to store this all 32 combination in 32 bit regesiter and
then want to comapre.

even i donot know like in VHDL how to defined internal signal in
Verilog?do i need to define internal signal in module?do i need to
define data type to internal signal?if yes then what data type i ahve
to use?wire or reg?

when I am suing assign out= a & b as an internal signal and that i
ahve to use further to comapre my input how i will do this?

Kindly go through my code(I ahve developed for one 20 bit phit) and
let me know where i am doing mistake

Module
test_packet1(a,b,c,d,e,f,packet_out,sub_file1,sub_field2,sub_filed_3,
sub_filed4,sub_file5,sub_file6,sub_filed7,sub_filed8,clk);

input [31:0] a,b,c,d,e,f;
input sub_file1,sub_field2;
input [2:0] sub_field3;
input [1:0] sub_field4;
input [3:0] sub_field5;
input [3:0] sub_field6;
input [1:0] sub_field7;
input [2:0] sub_field8;
ouput [19:0] packet_out;

wire [31:0] a,b,c,d,e,f;
wire sub_file1,sub_field2;
wire [2:0] sub_field3;
wire [1:0] sub_field4;
wire [3:0] sub_field5;
wire [3:0] sub_field6;
wire [1:0] sub_field7;
wire [2:0] sub_field8;
reg [19:0] packet_out;

//Internal signal and 35 bit wise AND combination store in this
reg(here i have question do i need to define this internal signal as
eg or wire?)

wire [31:0] out
0,out1,out2,out3,out4,out5,out6........................out35(I am not
writing the whole code)
//35 AND combination of 6 variable

assign out0 = a & b;
assign out0 = a & b;
assign out1 = a & c;
assign out2 = a & d;
assign out3 = a & e;
assign out4 = a & f;
assign out5 = a & b & c;

assign out6 = a & b & d;
assign out7 = a & b & e;
assign out8 = a & b & f;
assign out9 = a & b & c & d;
..
..
..
..
..
assign out 35 = e & f;

//here the actual code start

always @ (posedge clk)
begin
if (sub_field1 == out 0 || sub_field1 == out1 || sub_field1 ==
out2.................|| sub_filed1 == out 35 ) begin
packet_out[0]<= sub_field1;
else
begin
packet_out[0]<= packet_out[0];
sub_field1<= sub_field1;
end
end
if(sub_field2 == out0 || sub_filed2 == out1................sub_filed2
== out 35)begin
packet_out[1]<= sub_field2;
else
begin
packet_out[1]<=packet_out[1];
sub_field2<= sub_filed2;
end
end
..
..
..
..
..

if(sub_field8 == out0 || sub_filed8 == out1................sub_filed8
== out 35)begin
packet_out[19:17]<= sub_field2;
else
begin
packet_out[19:17]<=packet_out[19:17];
sub_field8<=sub_field8;
end
end
end module

kindly let me know where i am doing mistake?as I want to comapre each
filed with each 35 combination and sub_field matched with any
combination it will gives the output to the define packet bits.

kindly help me as i am stuck with this.
verilog_maan

 

On Oct 5, 9:46 pm, Verilog_Maan <mansipat...@gmail.com> wrote:

Hello All

I am designing packet header and I am stuck with very
simple problem and I an beginer of Verilog so I need your help.

packet is made up 80 bit and this 80 bit is devided into 20 bit phit
and this each phit is made up of various sub filed.I want to comapre
each sub filed with each 32 AND(bit wise AND) combination of 6
variable each is 32 bit long.how i will do?[Note:this filed varies
between 2 bits to 15 bits. In short i am doing mask and match].here is
my code and i am not getting the ouput so please help me with this.I
know i have to use byte comparator but how?
i also want to store this all 32 combination in 32 bit regesiter and
then want to comapre.

even i donot know like in VHDL how to defined internal signal in
Verilog?do i need to define internal signal in module?do i need to
define data type to internal signal?if yes then what data type i ahve
to use?wire or reg?

when I am suing assign out= a & b as an internal signal and that i
ahve to use further to comapre my input how i will do this?

Kindly go through my code(I ahve developed for one 20 bit phit) and
let me know where i am doing mistake

Module
test_packet1(a,b,c,d,e,f,packet_out,sub_file1,sub_field2,sub_filed_3,
sub_filed4,sub_file5,sub_file6,sub_filed7,sub_filed8,clk);

input [31:0] a,b,c,d,e,f;
input sub_file1,sub_field2;
input [2:0] sub_field3;
input [1:0] sub_field4;
input [3:0] sub_field5;
input [3:0] sub_field6;
input [1:0] sub_field7;
input [2:0] sub_field8;
ouput [19:0] packet_out;

wire [31:0] a,b,c,d,e,f;
wire sub_file1,sub_field2;
wire [2:0] sub_field3;
wire [1:0] sub_field4;
wire [3:0] sub_field5;
wire [3:0] sub_field6;
wire [1:0] sub_field7;
wire [2:0] sub_field8;
reg [19:0] packet_out;

//Internal signal and 35 bit wise AND combination store in this
reg(here i have question do i need to define this internal signal as
eg or wire?)

wire [31:0] out
0,out1,out2,out3,out4,out5,out6........................out35(I am not
writing the whole code)
//35 AND combination of 6 variable

assign out0 = a & b;
assign out0 = a & b;
assign out1 = a & c;
assign out2 = a & d;
assign out3 = a & e;
assign out4 = a & f;
assign out5 = a & b & c;

assign out6 = a & b & d;
assign out7 = a & b & e;
assign out8 = a & b & f;
assign out9 = a & b & c & d;
.
.
.
.
.
assign out 35 = e & f;

//here the actual code start

always @ (posedge clk)
begin
if (sub_field1 == out 0 || sub_field1 == out1 || sub_field1 ==
out2.................|| sub_filed1 == out 35 ) begin
packet_out[0]<= sub_field1;
else
begin
packet_out[0]<= packet_out[0];
sub_field1<= sub_field1;
end
end
if(sub_field2 == out0 || sub_filed2 == out1................sub_filed2
== out 35)begin
packet_out[1]<= sub_field2;
else
begin
packet_out[1]<=packet_out[1];
sub_field2<= sub_filed2;
end
end
.
.
.
.
.

if(sub_field8 == out0 || sub_filed8 == out1................sub_filed8
== out 35)begin
packet_out[19:17]<= sub_field2;
else
begin
packet_out[19:17]<=packet_out[19:17];
sub_field8<=sub_field8;
end
end
end module

kindly let me know where i am doing mistake?as I want to comapre each
filed with each 35 combination and sub_field matched with any
combination it will gives the output to the define packet bits.

kindly help me as i am stuck with this.
verilog_maan

HI,
1.I have one doubt in your explanation you have written.
with which value you are comparing 20 bit sub filed.
I did not that get that one can you explain clearly?
2.If you are thinking you are comparing 20 bit subfiled with 32 bit
pattern, with which 20 bits in pattern you are comparing?
3.You have mentioned the masking. If u are doing masking on which data
you are apply masking?
Can u once explain the problem clearly.. Surely i will get back to you.

 

[Verilog_Maan]

hello vishnu..

thanks for your reply...but my problem is solved..but
here is the answer of your question..

1) as i mentioned in my previous discription....my input will be
stream of 80 bit (1 flit)..and i am going to develop code such a way
that let say start from LSB to MSB..so it will comapre the first 4
bit[3:0] with the patttern in the 32 bit register if it matches then
will store in 80 bit register and will give output..

in short my 80 bit is divided in to 4 20-bit chunk and each chunk is
made of various sub field...
i hope you got my point..
vishnuprasa...@gmail.com wrote:

On Oct 5, 9:46 pm, Verilog_Maan <mansipat...@gmail.com> wrote:
Hello All

I am designing packet header and I am stuck with very
simple problem and I an beginer of Verilog so I need your help.

packet is made up 80 bit and this 80 bit is devided into 20 bit phit
and this each phit is made up of various sub filed.I want to comapre
each sub filed with each 32 AND(bit wise AND) combination of 6
variable each is 32 bit long.how i will do?[Note:this filed varies
between 2 bits to 15 bits. In short i am doing mask and match].here is
my code and i am not getting the ouput so please help me with this.I
know i have to use byte comparator but how?
i also want to store this all 32 combination in 32 bit regesiter and
then want to comapre.

even i donot know like in VHDL how to defined internal signal in
Verilog?do i need to define internal signal in module?do i need to
define data type to internal signal?if yes then what data type i ahve
to use?wire or reg?

when I am suing assign out= a & b as an internal signal and that i
ahve to use further to comapre my input how i will do this?

Kindly go through my code(I ahve developed for one 20 bit phit) and
let me know where i am doing mistake

Module
test_packet1(a,b,c,d,e,f,packet_out,sub_file1,sub_field2,sub_filed_3,
sub_filed4,sub_file5,sub_file6,sub_filed7,sub_filed8,clk);

input [31:0] a,b,c,d,e,f;
input sub_file1,sub_field2;
input [2:0] sub_field3;
input [1:0] sub_field4;
input [3:0] sub_field5;
input [3:0] sub_field6;
input [1:0] sub_field7;
input [2:0] sub_field8;
ouput [19:0] packet_out;

wire [31:0] a,b,c,d,e,f;
wire sub_file1,sub_field2;
wire [2:0] sub_field3;
wire [1:0] sub_field4;
wire [3:0] sub_field5;
wire [3:0] sub_field6;
wire [1:0] sub_field7;
wire [2:0] sub_field8;
reg [19:0] packet_out;

//Internal signal and 35 bit wise AND combination store in this
reg(here i have question do i need to define this internal signal as
eg or wire?)

wire [31:0] out
0,out1,out2,out3,out4,out5,out6........................out35(I am not
writing the whole code)
//35 AND combination of 6 variable

assign out0 = a & b;
assign out0 = a & b;
assign out1 = a & c;
assign out2 = a & d;
assign out3 = a & e;
assign out4 = a & f;
assign out5 = a & b & c;

assign out6 = a & b & d;
assign out7 = a & b & e;
assign out8 = a & b & f;
assign out9 = a & b & c & d;
.
.
.
.
.
assign out 35 = e & f;

//here the actual code start

always @ (posedge clk)
begin
if (sub_field1 == out 0 || sub_field1 == out1 || sub_field1 ==
out2.................|| sub_filed1 == out 35 ) begin
packet_out[0]<= sub_field1;
else
begin
packet_out[0]<= packet_out[0];
sub_field1<= sub_field1;
end
end
if(sub_field2 == out0 || sub_filed2 == out1................sub_filed2
== out 35)begin
packet_out[1]<= sub_field2;
else
begin
packet_out[1]<=packet_out[1];
sub_field2<= sub_filed2;
end
end
.
.
.
.
.

if(sub_field8 == out0 || sub_filed8 == out1................sub_filed8
== out 35)begin
packet_out[19:17]<= sub_field2;
else
begin
packet_out[19:17]<=packet_out[19:17];
sub_field8<=sub_field8;
end
end
end module

kindly let me know where i am doing mistake?as I want to comapre each
filed with each 35 combination and sub_field matched with any
combination it will gives the output to the define packet bits.

kindly help me as i am stuck with this.
verilog_maan

HI,
1.I have one doubt in your explanation you have written.
with which value you are comparing 20 bit sub filed.
I did not that get that one can you explain clearly?
2.If you are thinking you are comparing 20 bit subfiled with 32 bit
pattern, with which 20 bits in pattern you are comparing?
3.You have mentioned the masking. If u are doing masking on which data
you are apply masking?
Can u once explain the problem clearly.. Surely i will get back to you.

 

[glen herrmannsfeldt]

Verilog_Maan wrote:

I am designing packet header and I am stuck with very
simple problem and I an beginer of Verilog so I need your help.

The first thing to do in most cases is to consider how you might
implement the desired logic in TTL gates (or 74HCT if you like).

At this point, you should think about which things must be done
in parallel (separate blocks of gates), and which can be done
sequentially (shift registers, multiplexers, etc.).

packet is made up 80 bit and this 80 bit is devided into 20 bit phit
and this each phit is made up of various sub filed.I want to comapre
each sub filed with each 32 AND(bit wise AND) combination of 6
variable each is 32 bit long.how i will do?[Note:this filed varies
between 2 bits to 15 bits. In short i am doing mask and match].here is
my code and i am not getting the ouput so please help me with this.I
know i have to use byte comparator but how?
i also want to store this all 32 combination in 32 bit regesiter and
then want to comapre.

This sounds like a software implementation. In software with 32 bit
registers you need AND to select the appropriate bits. In verilog you
can set any width you need and avoid extra comparators.

even i donot know like in VHDL how to defined internal signal in
Verilog?do i need to define internal signal in module?do i need to
define data type to internal signal?if yes then what data type i ahve
to use?wire or reg?

wire for use with assign (continuous assignment) reg for behavioral
assignment (inside an always block).

when I am suing assign out= a & b as an internal signal and that i
ahve to use further to comapre my input how i will do this?

Kindly go through my code(I ahve developed for one 20 bit phit) and
let me know where i am doing mistake

Module
test_packet1(a,b,c,d,e,f,packet_out,sub_file1,sub_field2,sub_filed_3,
sub_filed4,sub_file5,sub_file6,sub_filed7,sub_filed8,clk);

input [31:0] a,b,c,d,e,f;
input sub_file1,sub_field2;
input [2:0] sub_field3;
input [1:0] sub_field4;
input [3:0] sub_field5;
input [3:0] sub_field6;
input [1:0] sub_field7;
input [2:0] sub_field8;
ouput [19:0] packet_out;

wire [31:0] a,b,c,d,e,f;
wire sub_file1,sub_field2;
wire [2:0] sub_field3;
wire [1:0] sub_field4;
wire [3:0] sub_field5;
wire [3:0] sub_field6;
wire [1:0] sub_field7;
wire [2:0] sub_field8;

If they are already input or output they don't need
to be declared wire. For behavioral outputs you do
need to still declare them reg.

packet_out;

//Internal signal and 35 bit wise AND combination store in this
reg(here i have question do i need to define this internal signal as
eg or wire?)

wire [31:0] out
0,out1,out2,out3,out4,out5,out6........................out35(I am not
writing the whole code)
//35 AND combination of 6 variable

assign out0 = a & b;
assign out0 = a & b;
assign out1 = a & c;
assign out2 = a & d;
assign out3 = a & e;
assign out4 = a & f;
assign out5 = a & b & c;

assign out6 = a & b & d;
assign out7 = a & b & e;
assign out8 = a & b & f;
assign out9 = a & b & c & d;

assign out 35 = e & f;

//here the actual code start

always @ (posedge clk)

I try not to mix behavioral and continuous assign logic so much,
except that flip-flops have to be in behavioral logic.

begin
if (sub_field1 == out 0 || sub_field1 == out1 || sub_field1 ==
out2.................|| sub_filed1 == out 35 ) begin

sub_filed1 is one bit, out0 through out35 are 32 bits.
Which bit is it supposed to compare?

<= sub_field1;
else
begin
packet_out[0]<= packet_out[0];
sub_field1<= sub_field1;
end
end
if(sub_field2 == out0 || sub_filed2 == out1................sub_filed2
== out 35)begin
packet_out[1]<= sub_field2;
else
begin
packet_out[1]<=packet_out[1];
sub_field2<= sub_filed2;
end
end

I think you are still thinking in terms of a serial computer
language. You should try to think more like wires and gates.

-- glen