packet generation

hi,
currently i am using cadence IUS 5.5,in systemverilog this version
doesn't support features like class,struct,union etc..
actually i have to generate the packet using Systemverilog.anybody
help me out ??

 

[Srinivasan Venkataramanan]

Hi,
If you "have to generate the packet using Systemverilog" - I suggest you
look at tools that support SystemVerilog today. Needless to say, VCS does
this today!

Sri
P.S. Sorry for this "marketing style" post - what else do you do when some
one presents a set of confllicting constraints?

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
<bharathiii@rediffmail.com> wrote in message
news:1121753427.575364.222230@g44g2000cwa.googlegroups.com...

hi,
currently i am using cadence IUS 5.5,in systemverilog this version
doesn't support features like class,struct,union etc..
actually i have to generate the packet using Systemverilog.anybody
help me out ??