Package constants (VHDL)

[Fred]

Historically I have used a VHDL file to embody the constants in a
design where possible using meaningful names which can be easily
changed.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
package constants is
constant rck_freq : integer := 30;
end constants;

I require two sets of constants according to debug or otherwise, I
might try:

package constants is
if debug = 1 then
constant rck_freq : integer := 10;
else
constant rck_freq : integer := 30;
end if;
end constants;

But ISE coughs. Can someone enlighten me on the correct way of doing
this, if possible?

 

[KJ]

On May 30, 10:34 am, Fred <fred__blo...@lycos.com> wrote:

I require two sets of constants according to debug or otherwise, I
might try:

package constants is
  if debug = 1 then
      constant rck_freq : integer := 10;
   else
      constant rck_freq : integer := 30;
   end if;
end constants;

But ISE coughs.  Can someone enlighten me on the correct way of doing
this, if possible?

Create a function that implements the selection...
function sel(Cond: Boolean; If_True, If_False: integer) return
integer;

Then use the function to set the constant...
constant rck_freq : integer := sel(Cond =>debug = 1, If_True => 10,
If_False =>30);

You'll likely find the 'sel' function to be very useful for simple
2=>1 muxing operations that you will also find it useful to override
the function with various other forms...
function sel(Cond: Boolean; If_True, If_False: std_logic) return
std_logic;
function sel(Cond: Boolean; If_True, If_False: std_logic_vector)
return std_logic_vector;
function sel(Cond: Boolean; If_True, If_False: std_ulogic_vector)
return std_ulogic_vector;
etc...

Kevin Jennings

 

[Fred]

On May 30, 3:58 pm, KJ <kkjenni...@sbcglobal.net> wrote:

Create a function that implements the selection...
function sel(Cond: Boolean; If_True, If_False: integer) return
integer;

Then use the function to set the constant...
constant rck_freq : integer := sel(Cond =>debug = 1, If_True => 10,
If_False =>30);

You'll likely find the 'sel' function to be very useful for simple
2=>1 muxing operations that you will also find it useful to override
the function with various other forms...
function sel(Cond: Boolean; If_True, If_False: std_logic) return
std_logic;
function sel(Cond: Boolean; If_True, If_False: std_logic_vector)
return std_logic_vector;
function sel(Cond: Boolean; If_True, If_False: std_ulogic_vector)
return std_ulogic_vector;
etc...

Many thanks indeed for such a quick reply. It's now sorted.

There are times when I don't find VHDL very instinctive and confess
I'm not very au fait with functions. Many thanks again.