<P_I_CLK> has illegal connection

[zlotawy]

I have two components. I cant deliver the same main clock to both. I have
error:

ERROR:Xst:2035 - Port &lt;P_I_CLK&gt; has illegal connection. Port is connected to
input buffer and following ports:
Port C of instance ii1/ii_item2/SIG_INT_REGS_0 in unit top11 with type
FDCE
CPU : 29.95 / 30.33 s | Elapsed : 30.00 / 30.00 s


Structure is:

1.top
2.component one
2.component two


If anyone of second delete, all is correct.

Component one consists dcm,
I tried use bugp but no result.

May You help me?

Thanks,zlotawy

 

[Symon]

"zlotawy" &lt;paraliczb@NO_SPAM_orange.pl&gt; wrote in message
news:fnpsvm$9se$1@inews.gazeta.pl...

I have two components. I cant deliver the same main clock to both. I have
error:

ERROR:Xst:2035 - Port &lt;P_I_CLK&gt; has illegal connection. Port is connected
to input buffer and following ports:
Port C of instance ii1/ii_item2/SIG_INT_REGS_0 in unit top11 with type
FDCE
CPU : 29.95 / 30.33 s | Elapsed : 30.00 / 30.00 s


May You help me?

Thanks,zlotawy

Hi zlotawy ,

You appear to be trying to attach a FDCE's clock pin to a pad. You can't do
that, you need an input buffer to take the signal from the pad to your
circuit. Instantiate an IBUF.
HTH., Syms.
p.s. And you'll have more success in future if you post FPGA specific
questions to comp.arch.fpga
p.p.s. And learn to STFW. Google this:-
"Port is connected to input buffer and following ports"