P&R based on the post-map simulation model?

[chifalcon]

Hi,
I need to modify the netlist generated from "Generate Post-map simulatio
model"(i.e. netgen).

After the netlist modifcation, can I continue the work of place&rout
based on the modified simulation model netlist?

Thanks!

Eric


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[RCIngham]

Hi,
I need to modify the netlist generated from "Generate Post-ma
simulation
model"(i.e. netgen).

After the netlist modifcation, can I continue the work of place&route
based on the modified simulation model netlist?

Thanks!

Eric


---------------------------------------
Posted through http://www.FPGARelated.com

Short answer: no.

Why do you need to modify the post-map SIMULATION netlist?


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[NeedCleverHandle]

On Jun 22, 9:45 am, "chifalcon"
<eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:

Hi,
  I need to modify the netlist generated from "Generate Post-map simulation
model"(i.e. netgen).

  After the netlist modifcation, can I continue the work of place&route
based on the modified simulation model netlist?

  Thanks!

  Eric

---------------------------------------        
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Long answer: You can't Place & Route a *simulation* netlist, before
or after modification.

 

[Andreas Ehliar]

On 2011-06-22, chifalcon <eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:

Hi,
I need to modify the netlist generated from "Generate Post-map simulation
model"(i.e. netgen).

After the netlist modifcation, can I continue the work of place&route
based on the modified simulation model netlist?

As the other posters have already said, it is not really possible to do what
you are asking.

However, you can do something similar by modifying the post map NCD file.
The key is to convert the NCD file into ASCII format in the form of an XDL
netlist.

You can do this using the xdl command from xilinx with the -ncd2xdl and
-xdl2ncd switches.

Another way of doing this is to open the mapped NCD file in the FPGA editor
and create a script that does the modification. Then you can use fpga_edline
to execute the script in batch mode.

I wouldn't recommend this though unless you have some really good reason
for doing this. The main use case I've seen so far is to merge debug tools
such as a logic analyzer into the design after synthesis is complete so that
you don't need to rerun synthesis every time you wish to connect different
signals to your logic analyzer. (In previous versions of ISE it was actually
possible to do this kind of merging after place and route, but I haven't
found a good way of doing this in newer versions of ISE. [1])

regards
/Andreas

[1] In earlier versions you could give a partially routed NCD file to par
and tell it to just route the remaining wires. This does not seem possible
to do any longer unfortunately...