OVL assertion problem

[Haja]

Hello,
I am trying to write some OVL assertion in my Verilog design. I am
using ModelSim6.2i that comes with ispLever from Lattice. I wrote a
simple assertion like
assert_never assertion1 (CLK, RSTN, (A==B));

I got the following error when loading the design for simulation:
"Instantiation of 'assert_never' failed. The design unit was not
found."

Is there any setup that I need to make. I presume that OVL library is
pre-compiled. Am I overlooking something!

Haja