OVL assertion for double SOP event

Guest
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.


ThankX,
NAHUM
 
Hi Nahum,
Are you open to a better solution than OVL for this? Here is
PSL code for you. Given that majority of tools support SVA/PSL today,
this should get you going. Doing things like this in OVL is hard (if
not impossible).

assert always
rose(sop) |=> eop before sop @ (posedge clk);

(I didn't verify it, this code should give you the idea to get it
working).

HTH
Ajeetha, CVC
www.noveldv.com

nahum_barnea@yahoo.com wrote:
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.


ThankX,
NAHUM
Click to expand...
 
I agree with Ajeetha that OVL does not have support to check
overlapping events.

However, simple FSM-like verilog code can check this condition:

reg state = 0;
always @(posedge clk)
if (sop & !state) state <= 1;
else if (eop & state) state <= 0;
else if (sop & state) $display ("ERROR: no eop between 2 sop");


Regards,
Alex

nahum_barnea@yahoo.com wrote:
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.


ThankX,
NAHUM
Click to expand...
 
Thanks for the response.
Can you write it in SVA as well ??

I understand that psl rose can be implemented with $rose
and thet '=>' has the same meaning in SVA,
but I did'nt find any SVA compatible solution to the 'before' clause.


Ajeetha wrote:
Hi Nahum,
Are you open to a better solution than OVL for this? Here is
PSL code for you. Given that majority of tools support SVA/PSL today,
this should get you going. Doing things like this in OVL is hard (if
not impossible).

assert always
rose(sop) |=> eop before sop @ (posedge clk);

(I didn't verify it, this code should give you the idea to get it
working).

HTH
Ajeetha, CVC
www.noveldv.com

nahum_barnea@yahoo.com wrote:
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.


ThankX,
NAHUM
Click to expand...
 
In SVA, one could write:

$rose(sop) |=> !sop throughout (eop[->1]);

Untested, incomplete code - quick idea of sorts. We show another
approach in our SVA Handbook, see www.abv-sva.org


HTH
Ajeetha, CVC
www.noveldv.com


nahum_barnea@yahoo.com wrote:
Thanks for the response.
Can you write it in SVA as well ??

I understand that psl rose can be implemented with $rose
and thet '=>' has the same meaning in SVA,
but I did'nt find any SVA compatible solution to the 'before' clause.


Ajeetha wrote:
Hi Nahum,
Are you open to a better solution than OVL for this? Here is
PSL code for you. Given that majority of tools support SVA/PSL today,
this should get you going. Doing things like this in OVL is hard (if
not impossible).

assert always
rose(sop) |=> eop before sop @ (posedge clk);

(I didn't verify it, this code should give you the idea to get it
working).

HTH
Ajeetha, CVC
www.noveldv.com

nahum_barnea@yahoo.com wrote:
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.


ThankX,
NAHUM
Click to expand...
 
nahum_barnea@yahoo.com wrote:
Hi.

I want to write an assertion using OVL that will assert an error if
there are 2 clock cycles where SOP signal is '1' and between these
clock cycles there was never a clock cycle where EOP signal is '1'.

[snip]
Click to expand...

What's SOP and EOP signal mean?

Thanks!
Davy

ThankX,
NAHUM
Click to expand...
 
Mike Treseler 写道：

Davy wrote:

What's SOP and EOP signal mean?

start | end of packet
(utopia bus)
Click to expand...
Hi,

Can you tell me utopia bus is what bus? Thanks!

Davy
 
Davy wrote:

Can you tell me utopia bus is what bus? Thanks!
Click to expand...
It's a bus for packetized data.
Here's a recent derivative:
http://www.altera.com/literature/fs/fs_atlantic.pdf

-- Mike Treseler
 
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