B
Bill Valores
Guest
Hello,
In Verilog, it's possible to write several (non-blocking) procedural
assignments in the same always statement. This will work in
simulations of course, with the last acted upon assignment giving the
final value. The question is if this is SAFE PRACTICE when writing
code for synthesis.
The example below works on the Xilinx XST synthesizer, but can I rely
on this to be portable? Is this coding style mainstream enough to use
with no worries?
always @(posedge clk)
begin
in_special_state <= 0; // Default value
case (state)
(...)
ST_special_state:
begin
state <= ST_next;
in_special_state <= 1;
end
(...)
endcase
if (now_special)
state <= ST_special_state;
end
Note that I did two things in the example above:
(1) Gave "in_special_state" a default value which is overridden by the
case statement only when it's a certain state. So the register goes
high only when explicitly set in the case statement, saving the need
to turn it off in the following state.
(2) Wrote an overriding rule for "state" after the case statement. You
may ask why not writing an "if" statement before the state machine.
This was necessary when "now_special" had the function of a reset
signal, which moves to the initial state, which in turn resets several
registers. Since the invocation of this state could be from the state
machine itself, these register resets had to be within the case
statement. Had I used an "if" statement for "now_special" and put the
case in that if's "else", then I'd have to repeat these register
resets in the "if (now_special)" clause. Code which has to be repeated
consistently = source for bugs.
Experiences and insights, anyone?
Thanks,
Bill
In Verilog, it's possible to write several (non-blocking) procedural
assignments in the same always statement. This will work in
simulations of course, with the last acted upon assignment giving the
final value. The question is if this is SAFE PRACTICE when writing
code for synthesis.
The example below works on the Xilinx XST synthesizer, but can I rely
on this to be portable? Is this coding style mainstream enough to use
with no worries?
always @(posedge clk)
begin
in_special_state <= 0; // Default value
case (state)
(...)
ST_special_state:
begin
state <= ST_next;
in_special_state <= 1;
end
(...)
endcase
if (now_special)
state <= ST_special_state;
end
Note that I did two things in the example above:
(1) Gave "in_special_state" a default value which is overridden by the
case statement only when it's a certain state. So the register goes
high only when explicitly set in the case statement, saving the need
to turn it off in the following state.
(2) Wrote an overriding rule for "state" after the case statement. You
may ask why not writing an "if" statement before the state machine.
This was necessary when "now_special" had the function of a reset
signal, which moves to the initial state, which in turn resets several
registers. Since the invocation of this state could be from the state
machine itself, these register resets had to be within the case
statement. Had I used an "if" statement for "now_special" and put the
case in that if's "else", then I'd have to repeat these register
resets in the "if (now_special)" clause. Code which has to be repeated
consistently = source for bugs.
Experiences and insights, anyone?
Thanks,
Bill